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參數資料
| 型號： | SST28SF040A-120-4CPH |
| 英文描述： | Capacitor; Capacitance [nom]: 1000uF ; Working Voltage (Vdc)[max]: 415V; Capacitance Tolerance: +/-20%; Dielectric: Aluminum Electrolytic; Temperature Range: -40°C to +85°C; Lead Style: Screw Terminal (Clamp Mount); Body Dimensions: 51x105mm |
| 中文描述： | 集成電路4MB的5V的快閃記憶體 |
| 文件頁數： | 3/28頁 |
| 文件大小： | 280K |
| 代理商： | SST28SF040A-120-4CPH |
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3
2000 Silicon Storage Technology, Inc.
310-3 6/00
4 Megabit SuperFlash EEPROM
SST28SF040A / SST28VF040A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data Sheet
Read
The Read operation is initiated by setting CE#, and OE#
to logic low and setting WE# to logic high (See Table 2).
See Figure 3 for Read cycle timing waveform. The Read
operation from the host retrieves data from the array. The
device remains enabled for Read until another operation
mode is accessed. During initial power-up, the device is
in the Read mode and is Software Data protected. The
device must be unprotected to execute a Write com-
mand.
The Read operation of the SST28SF040A/28VF040A
are controlled by OE# and CE# at logic low. When CE #
is high, the chip is deselected and only standby power will
be consumed. OE# is the output control and is used to
gate data from the output pins. The data bus is in high
impedance state when CE# or OE# are high.
Read-ID operation
The Read-ID operation is initiated by writing a single
command (90H). A read of address 0000H will output the
manufacturer’s code (BFH). A read of address 0001H
will output the device code (04H). Any other valid com-
mand will terminate this operation.
Data Protection
In order to protect the integrity of nonvolatile data stor-
age, the SST28SF040A/28VF040A provide both
hardware and software features to prevent inadvertent
writes to the device, for example, during system power-
up or power-down. Such provisions are described below.
Hardware Data Protection
The SST28SF040A/28VF040A are designed with hard-
ware features to prevent inadvertent writes. This is done
in the following ways:
1.
Write Cycle Inhibit Mode: OE# low, CE#, or WE#
high will inhibit the Write operation.
2.
Noise/Glitch Protection: A WE# pulse width of less
than 5 ns will not initiate a Write cycle.
3.
V
CC
Power Up/Down Detection: The Write operation
is inhibited when V
CC
is less than 2.0V.
4.
After power-up the device is in the Read mode and
the device is in the Software Data Protect state.
Software Data Protection (SDP)
The SST28SF040A/28VF040A have software methods
to further prevent inadvertent writes. In order to perform
an Erase or Program operation, a two-step command
sequence consisting of a set-up command followed by
an execute command avoids inadvertent erasing and
programming of the device.
The SST28SF040A/28VF040A will default to Software
Data Protection after power up. A sequence of seven
consecutive reads at specific addresses will unprotect
the device The address sequence is 1823H, 1820H,
1822H, 0418H, 041BH, 0419H, 041AH. The address
bus is latched on the rising edge of OE# or CE#, which-
ever occurs first. A similar seven read sequence of
1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 040AH
will protect the device. Also refer to Figures 9 and 10 for
the 7 read cycle sequence Software Data Protection.
The I/O pins can be in any state (i.e., high, low, or
tristate).
Write Operation Status Detection
The SST28SF040A/28VF040A provide three means to
detect the completion of a Write operation, in order to
optimize the system Write operation. The end of a Write
operation (Erase or Program) can be detected by three
means: 1) monitoring the Data# Polling bit; 2) monitoring
the Toggle bit; or 3) by two successive reads of the same
data. These three detection mechanisms are described
below.
The actual completion of the nonvolatile Write is asyn-
chronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with the DQ
used. In order to prevent
spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the ac-
cessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the rejection is valid.
Data# Polling (DQ
7
)
The SST28SF040A/28VF040A feature Data# Polling to
indicate the Write operation status. During a Write opera-
tion, any attempt to read the last byte loaded during the
byte-load cycle will receive the complement of the true
data on DQ
7
. Once the Write cycle is completed, DQ
7
will
show true data. The device is then ready for the next
operation. See Figure 11 for Data# Polling timing wave-
forms. In order for Data# Polling to function correctly , the
byte being polled must be erased prior to programming.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SST28SF040A-120-4C-PH | 功能描述:電可擦除可編程只讀存儲器 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| SST28SF040A-120-4C-WH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit (512K x8) SuperFlash EEPROM |
| SST28SF040A-120-4I-EH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit (512K x8) SuperFlash EEPROM |
| SST28SF040A-120-4I-NH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit (512K x8) SuperFlash EEPROM |
| SST28SF040A-120-4I-PH | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:4 Mbit (512K x8) SuperFlash EEPROM |
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