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參數(shù)資料
| 型號： | SST89V54RD2-33-C-NJE |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 28/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 24KB FLASH 44PLCC |
| 標準包裝： | 26 |
| 系列： | FlashFlex® |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 8K x 8 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 44-LCC |
| 包裝： | 管件 |
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2011 Silicon Storage Technology, Inc.
DS25087A
10/11
34
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Flash Memory Programming
The device internal flash memory can be programmed or erased using the In-Application Programming
(IAP) mode.
Product Identification
The Read-ID command accesses the Signature Bytes that identify the device and the manufacturer as
SST. External programmers primarily use these Signature Bytes in the selection of programming algo-
rithms.
In-Application Programming Mode
The device offers either 24/40 KByte of in-application programmable flash memory. During in-applica-
tion programming, the CPU of the microcontroller enters IAP mode. The two blocks of flash memory
allow the CPU to execute user code from one block, while the other is being erased or reprogrammed
concurrently. The CPU may also fetch code from an external memory while all internal flash is being
reprogrammed. The mailbox registers (SFST, SFCM, SFAL, SFAH, SFDT and SFCF) located in the
special function register (SFR), control and monitor the device’s erase and program process.
Table 13 outline the commands and their associated mailbox register settings.
In-Application Programming Mode Clock Source
During IAP mode, both the CPU core and the flash controller unit are driven off the external clock.
However, an internal oscillator will provide timing references for Program and Erase operations. The
internal oscillator is only turned on when required, and is turned off as soon as the flash operation is
completed.
Memory Bank Selection for In-Application Programming Mode
With the addressing range limited to 16 bit, only 64 KByte of program address space is “visible” at any
one time. The bank selection (the configuration of EA# and SFCF[1:0]), allows Block 1 memory to be
overlaid on the lowest 8 KByte of Block 0 memory, making Block 1 reachable. The same concept is
employed to allow both Block 0 and Block 1 flash to be accessible to IAP operations. Code from a
block that is not visible may not be used as a source to program another address. However, a block
that is not “visible” may be programmed by code from the other block through mailbox registers.
The device allows IAP code in one block of memory to program the other block of memory, but may not
program any location in the same block. If an IAP operation originates physically from Block 0, the tar-
get of this operation is implicitly defined to be in Block 1. If the IAP operation originates physically from
Table 12: Product Identification
Address
Data
Manufacturer’s ID
30H
BFH
Device ID
SST89V54RD2/RD
31H
9EH
SST89V58RD2/RD
31H
9AH
T0-0.2 25087
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SST89V54RD2-33-C-NJE1 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89V54RD2-33-C-NJF2 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89V54RD2-33-C-PI | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89V54RD2-33-C-PIE1 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89V54RD2-33-C-PIF2 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
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