參數(shù)資料
型號(hào)： SSTUA32866EC/G,551
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
封裝： 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96
文件頁(yè)數(shù)： 25/28頁(yè)
文件大小： 153K
代理商： SSTUA32866EC/G,551
SSTUA32866_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
6 of 28
NXP Semiconductors
SSTUA32866
1.8 V DDR2-667 congurable registered buffer with parity
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Type
Description
GND
B3, B4, D3, D4,
F3, F4, H3, H4,
K3, K4, M3, M4,
P3, P4
ground input
ground
VDD
A4, C3, C4, E3,
E4, G3, G4, J3,
J4, L3, L4, N3,
N4, R3, R4, T4
1.8 V nominal
power supply voltage
VREF
A3, T3
0.9 V nominal
input reference voltage
CK
H1
Differential input
positive master clock input
CK
J1
Differential input
negative master clock input
C0
G6
LVCMOS inputs
Conguration control inputs; Register A
or Register B and 1 : 1 mode or
1 : 2 mode select.
C1
G5
RESET
G2
LVCMOS input
Asynchronous reset input (active LOW).
Resets registers and disables VREF data
and clock.
CSR
J2
SSTL_18 input
Chip select inputs (active LOW). Disables
D1 to D25[2] outputs switching when both
inputs are HIGH.
DCS
H2
D1 to D25
SSTL_18 input
Data input. Clocked in on the crossing of
the rising edge of CK and the falling edge
of CK.
DODT
SSTL_18 input
The outputs of this register bit will not be
suspended by the DCS and CSR control.
DCKE
SSTL_18 input
The outputs of this register bit will not be
suspended by the DCS and CSR control.
PAR_IN
G1
SSTL_18 input
Parity input. Arrives one clock cycle after
the corresponding data input.
Q1 to Q25,
Q2A to Q14A,
Q1B to Q14B
1.8 V CMOS
outputs
Data outputs that are suspended by the
DCS and CSR control[3].
PPO
A2
1.8 V CMOS
output
Partial parity out. Indicates odd parity of
inputs D1 to D25[2].
QCS, QCSA,
QCSB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
QODT, QODTA,
QODTB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
QCKE, QCKEA,
QCKEB
1.8 V CMOS
output
Data output that will not be suspended by
the DCS and CSR control.
相關(guān)PDF資料
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SSTUA32866EC/G,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
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SSTUA32S865BHLFT 功能描述:IC REGIST BUFF 25BIT DDR 160BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:- 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR)
SSTUA32S865ET 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications
SSTUA32S865ET,518 功能描述:寄存器 1.8V 28BT REGBUFF/PAR-DDR2-667 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
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