Notes: 1. CL incluces probe and jig" />
參數(shù)資料
型號(hào): SSTUB32872AHMLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/18頁
文件大?。?/td> 0K
描述: IC REGIST BUFF 28BIT DDR2 96-BGA
標(biāo)準(zhǔn)包裝: 2,500
邏輯類型: DDR2 的寄存緩沖器
電源電壓: 1.7 V ~ 1.9 V
位數(shù): 28
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 96-LFBGA
供應(yīng)商設(shè)備封裝: 96-CABGA(13.5x5.5)
包裝: 帶卷 (TR)
13
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR
≤10 MHz,
Zo=50
Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VREF = VDD/2
6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600 mV
9. tPLH and tPHL are the same as tPDM.
RL = 1000Ω
CL = 30 pF
(see Note 1)
LOAD CIRCUIT
tw
VICR
Inpu t
VIH
VIL
VOLTAGE WAVEFORMS – PULSE DURATION
VREF
Inpu t
tsu
th
VID
VICR
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
VICR
VID
VICR
Output
VOL
VOH
VTT
tPHL
tPLH
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
tRPHL
VOL
VOH
VIL
VIH
Output
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
VDD/2
VTT
tact
tinact
LVCMOS
Input
RST
VOLTAGE AND CURRENT WAVEFORMS
IDD
(see
Note 2)
90%
10%
INPUTS ACTIVE AND INACTIVE TIMES
0 V
VDD
Test Point
VDD/2
VCMOS
Inp ut
RST
TL=350ps, 50
Ω
DUT
CK
Out
TL=50
Ω
CK Inputs
VID
CK
RL = 100Ω
CK
Test Point
RL = 1000Ω
VDD
Figure 6
Parameter Measurement Information (V
= 1.8V 0.1V)
DD
±
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