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ST10F252M
Memory organization
XSSC: Address range 00’E800h - 00’E8FFh is reserved for the XSSC module access. The
XSSC is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON
register. Accesses to the XSSC module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100.0 ns at
40 MHz CPU clock. No tristate waitstate is used.
XI2C: Address range 00’EA00h - 00’EAFFh is reserved for the XI2C module access. The
XI2C is enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON
register. Accesses to the XI2C module use demultiplexed addresses and a 16-bit data bus
(only word accesses are possible). Two waitstates give an access time of 100.0 ns at
40 MHz CPU clock. No tristate waitstate is used.
X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set
of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON
register and bit10 of the XPERCON register. Accesses to these additional features use
demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two
waitstates give an access time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is
used. The following set of features are provided:
●
CLKOUT programmable divider
●
XBUS interrupt management registers
●
CAN2 multiplexing on P4.5/P4.6
●
CAN1-2 main clock prescaler
●
main voltage regulator disable for power-down mode
●
TTL / CMOS threshold selection for Port0, Port1, and Port5
●
Flash temporary unprotection
●
Port4/Port7 selection for pins 47-50
In order to keep the needs of designs where more memory is required than is provided on
the chip, up to 16 Mbytes of external memory can be connected to the microcontroller.
Note:
When P7EN bit is set in XMISC register, the Port7 low nibble is available on the pins 47 to
50 and Port4 low is not available. Therefore the relative address lines are not available and
the external memory space is reduced to 64 Kbytes."
Visibility of XBUS peripherals
In order to keep the ST10F252M compatible with ST10F168 / ST10F269, the XBUS
peripherals can be selected to be visible on the external address / data bus. Different bits for
X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the
global enabling with XPEN bit in SYSCON register, the corresponding address space, port
pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and
XPERCON and XPEREMU clock gating
As already mentioned, the XPERCON register has to be programmed to enable the single
X-BUS modules separately. The XPERCON is a read/write ESFR register.
The new feature of clock gating has been implemented by mean of this register. Once the
EINIT instruction has been executed, all the peripherals (except RAMs and XMISC), not
enabled in the XPERCON register are not be clocked. The clock gating can reduce power
consumption and improve EMI when the user doesn’t use all the X-Peripherals
Note:
When the clock has been gated in the disabled Peripherals, no Reset will be raised once the
EINIT instruction has been executed.