參數(shù)資料
型號: ST10F269Z2Q3
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144
封裝: 28 X 28 MM, PLASTIC, QFP-144
文件頁數(shù): 86/160頁
文件大小: 1541K
代理商: ST10F269Z2Q3
ST10F269
31/160
When the ST10F269 has entered BSL mode, the following configuration is automatically set (values that
deviate from the normal reset values, are marked):
In this case, the watchdog timer is disabled, so the
bootstrap loading sequence is not time limited.
Pin TXD0 is configured as output, so the
ST10F269 can return the identification Byte.
Even if the internal Flash is enabled, no code can
be executed out of it.
The hardware that activates the BSL during reset
may be a simple pull-down resistor on P0L.4 for
systems
that
use
this
feature
upon
every
hardware reset.
A switchable solution (via jumper or an external
signal)
can
be
used
for
systems
that
only temporarily use the bootstrap loader (see
Figure 6).
After
sending
the
identification
Byte
the
ASC0 receiver
is
enabled
and
is
ready
to
receive the initial 32 Bytes from the host. A half
duplex connection is therefore sufficient to feed
the BSL.
5.6.2 - Memory Configuration After Reset
The configuration (and the accessibility) of the
ST10F269’s
memory
areas
after
reset
in
Bootstrap-Loader mode differs from the standard
case. Pin EA is not evaluated when BSL mode is
selected, and accesses to the internal Flash area
are partly redirected, while the ST10F269 is in
BSL mode (see Figure 7). All code fetches are
made from the special Boot-ROM, while data
accesses read from the internal user Flash. Data
accesses
will
return
undefined
values
on
ROMless devices.
The code in the Boot-ROM is not an invariant
feature of the ST10F269. User software should
not try to execute code from the internal Flash
area while the BSL mode is still active, as these
fetches will be redirected to the Boot-ROM. The
Boot-ROM will also “move” to segment 1, when
the internal Flash area is mapped to segment 1
(see Figure 7).
Watchdog Timer:
Disabled
Register SYSCON:
0E00h
Context Pointer CP:
FA00h
Register STKUN:
FA40h
Stack Pointer SP:
FA40h
Register STKOV:
FA0Ch 0<->C
Register S0CON:
8011h
Register BUSCON0:
acc. to startup configuration
Register S0BG:
Acc. to ‘00’ Byte
P3.10 / TXD0:
‘1
DP3.10:
‘1
Figure 6 : Hardware Provisions to Activate the BSL
RPOL.4
8k
Circuit 1
POL.4
Normal Boot
BSL
External
Signal
RPOL.4
8k
Circuit 2
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