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參數(shù)資料
| 型號： | ST16-RFRDCS |
| 英文描述： | ST16-19RFRDCS CHIP SET INTERFACE SPECIFICATION |
| 中文描述： | 的ST16 - 19RFRDCS芯片組接口規(guī)范 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 146K |
| 代理商： | ST16-RFRDCS |
4/15
ST16-19RFRDCS
FSD_CHIPSET_B/0104VP2
Figure 3
FPGA read access chronogram for last byte
Before sending the last byte the FPGA takes the Rx_fifo_empty line high to indicate to the MCU that this
is the last data.
1.3.5 MCU interface timings
The following board provides interface timings (cf previous chronogram)
Table 1
: Interface timing
Timing
t0
Parameter
Min. (ns)
0
Max. (ns)
Rx_irq_eof to Mic_Strb_b Transition
Mic_Ctrl_Data, Mic_RW (and Mic_Data in writing) Setup Time before
Mic_Strb_b Low Transition
Mic_Ctrl_Data, Mic_RW (and Mic_Data in writing) Hold Time before
Mic_Strb_b High Transition
Mic_Strb_b Width Low (Activ)
Mic_Strb_b Width High (Inactiv)
Mic_Strb_b Activ to Valid Data in Reading
Mic_Strb_b Inactiv to Tri-States Data in Reading
t1
0
t2
0
t3
t4
t5
t6
240
80
240
20
Acquisition of the last byte
t6
t4
t3
Mic_Ctrl_Data
Mic_RW
Mic_Strb_b
Mic_Data(7:0)
Rx_fifo_empty
Rx_irq_eof
Tx_fifo_empty
Tx_start
t1
t2
t0
t5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST19-RFRDCS | ST16-19RFRDCS CHIP SET INTERFACE SPECIFICATION |
| ST16 | CHIP SET INTERFACE SPECIFICATION |
| ST16010 | 1-Mbit (128K x 8) Static RAM |
| ST16010A | 1-Mbit (128K x 8) Static RAM |
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