REV. 4.0.1 2.97V TO 5.5V DUART 7 2.5 INTA and INTB Outputs The INTA and INTB interrupt output changes according to the operating m" />
參數(shù)資料
型號(hào)： ST16C2450CQ-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 28/30頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR ST16C2450 48TQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
xr
ST16C2450
REV. 4.0.1
2.97V TO 5.5V DUART
7
2.5
INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 2 summarizes the operating behavior for the transmitter and receiver. Also see Figure 12 and Figure 13.
2.6
Crystal Oscillator or External Clock Input
The 2450 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. See “Programmable Baud Rate
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4), with an external 500 k
to
1 M
resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
TABLE 2: INTA AND INTB PINS OPERATION FOR TRANSMITTER
TRANSMITTER
RECEIVER
INTA/B Pin
0 = a byte in THR
1 = THR empty
0 = no data
1 = 1 byte
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
C1
22-47 pF
C2
22-47 pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500 Κ 1 Μ
XTAL1
XTAL2
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