REV. 4.4.1 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 2.11 Internal Loopback The C2550 UART provides an internal loopback capability fo" />
參數(shù)資料
型號: ST16C2550CQ-0B-EB
廠商: Exar Corporation
文件頁數(shù): 7/37頁
文件大小: 0K
描述: EVAL BOARD FOR ST16C2551 48TQFP
標(biāo)準(zhǔn)包裝: 1
系列: *
ST16C2550
15
REV. 4.4.1
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
2.11
Internal Loopback
The C2550 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Modem
/
G
en
eral
Purpos
e
Cont
rol
Logic
Inte
rn
a
lD
a
ta
Bus
L
ines
and
Co
ntrol
Signa
ls
RTSA#/RTSB#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2A#/OP2B#
VCC
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