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參數(shù)資料
| 型號： | ST16C2550CQ48TR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 5/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B DUAL 48TQFP |
| 標準包裝： | 1,500 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶故障啟動位檢測功能： | 是 |
| 帶調制解調器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X Clock
ST16C2550
13
REV. 4.4.1
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
2.9.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO MODE
Transmit Data Shift Register
(TSR)
Data Byte
THR Interrupt (ISR bit-1) when TX
FIFO becomes empty. FIFO is
enabled by FCR bit-0=1.
Transmit FIFO
16X Clock
TXFIFO1
THR
2.10
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C2550IJ44 | 制造商:Exar Corporation 功能描述: |
| ST16C2550IJ44-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550IJ44TR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 16Byte FIFO 3.3V/5V 44-Pin PLCC T/R 制造商:Exar Corporation 功能描述:ST16C2550IJ44TR-F |
| ST16C2550IP40 | 功能描述:UART 接口集成電路 DUAL UART W/16 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C2550IQ48 | 制造商:Rochester Electronics LLC 功能描述: |
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