REV. 4.4.1 2.97V TO 5.5V DUART WITH 16-BYTE FIFO MSR[7]: CD Input Status Normally this bit is the compliment of the CD# input. In " />
參數(shù)資料
型號(hào)： ST16C2550IQ48TR-F
廠商： Exar Corporation
文件頁數(shù)： 18/37頁
文件大小： 0K
描述： IC UART FIFO 16B DUAL 48TQFP
標(biāo)準(zhǔn)包裝： 1,500
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.97 V ~ 5.5 V
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 帶卷 (TR)
ST16C2550
25
REV. 4.4.1
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
MSR[7]: CD Input Status
Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.10
Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.11
Baud Rate Generator Registers (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’. See
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B
DLM
Bits 7-0 = 0xXX
DLL
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF
TX
Logic 1
OP2#
Logic 1
RTS#
Logic 1
DTR#
Logic 1
RXRDY#
Logic 1
TXRDY#
Logic 0
INT
Three-State Condition
REGISTERS
RESET STATE
I/O SIGNALS
RESET STATE
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