O TO O O TO
參數(shù)資料
型號: ST16C2552CJ44-F
廠商: Exar Corporation
文件頁數(shù): 20/34頁
文件大?。?/td> 0K
描述: IC UART FIFO 16B DUAL 44PLCC
標準包裝: 27
特點: *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 3.3 V ~ 5 V
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱: 1016-1257-5
AC ELECTRICAL CHARACTERISTICS
O TO
O
O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V
70 PF LOAD WHERE APPLICABLE
SYMBOL
PARAMETER
LIMITS
MIN
MAX
LIMITS
MIN
MAX
UNIT
-
Crystal Frequency
20
24
MHz
CLK
Clock Pulse Duration
17
8
ns
OSC
External Clock Frequency
30
64
MHz
TAS
Address Setup Time
5
0
ns
TAH
Address Hold Time
10
5
ns
TCS
Chip Select Width
66
50
ns
TRD
IOR# Strobe Width
35
25
ns
TDY
Read Cycle Delay
40
30
ns
TRDV
Data Access Time
35
25
ns
TDD
Data Disable Time
0
25
0
15
ns
TWR
IOW# Strobe Width
40
25
ns
TDY
Write Cycle Delay
40
30
ns
TDS
Data Setup Time
20
15
ns
TDH
Data Hold Time
5
ns
TWDO
Delay From IOW# To Output
50
40
ns
TMOD
Delay To Set Interrupt From MODEM Input
40
35
ns
TRSI
Delay To Reset Interrupt From IOR#
40
35
ns
TSSI
Delay From Stop To Set Interrupt
1
Bclk
TRRI
Delay From IOR# To Reset Interrupt
45
40
ns
TSI
Delay From Start To Interrupt
45
40
ns
TINT
Delay From Initial INT Reset To Transmit Start
8
24
8
24
Bclk
TWRI
Delay From IOW# To Reset Interrupt
45
40
ns
TSSR
Delay From Stop To Set RXRDY#
1
Bclk
TRR
Delay From IOR# To Reset RXRDY#
45
40
ns
TWT
Delay From IOW# To Set TXRDY#
45
40
ns
TSRT
Delay From Center of Start To Reset TXRDY#
8
Bclk
TRST
Reset Pulse Width
40
ns
N
Baud Rate Divisor
1
216-1
1
216-1
-
Bclk
Baud Clock
16X of data rate
Hz
ST16C2552
27
REV. 4.2.2
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
TA=0
70 C (-40
3.3
5.0
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