參數(shù)資料
型號(hào)： ST16C550CQ48-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 7/35頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 16B SGL 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
電源電壓： 2.97 V ~ 5.5 V
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤(pán)
其它名稱： 1016-1260
ST16C550
15
Rev. 5.01
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT 4-7: Not used and set to “0”.
FIFO Control Register (FCR)
This register is used to enable the FIFO’s, clear the
FIFO’s, set the transmit/receive FIFO trigger levels,
and select the DMA mode. The DMA, and FIFO
modes are defined as follows:
DMA MODE:
See description and DMA tables on page 11.
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This
bit must be a “1” when other FCR bits are written to or
they will not be programmed.
FCR BIT-1:
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the contents of the receive FIFO and
resets the FIFO counter logic (the receive shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the contents of the transmit FIFO and
resets the FIFO counter logic (the transmit shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condi-
tion)
Logic 1 = Set DMA mode “1.”
Transmit operation in mode “0”:
When the ST16C550 is in the ST16C450 mode
(FIFO’s disabled, FCR bit-0 = logic 0) or in the FIFO
mode (FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-
3 = logic 0) and when there are no characters in the
transmit FIFO or transmit holding register, the -
TXRDY pin will be a logic 0. Once active the -TXRDY
pin will go to a logic 1 after the first character is loaded
into the transmit holding register.
Receive operation in mode “0”:
When the ST16C550 is in mode “0” (FCR bit-0 = logic
0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit-
3 = logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode “1”:
When the ST16C550 is in FIFO mode ( FCR bit-0 =
logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be
a logic 1 when the transmit FIFO is completely full. It
will be a logic 0 if one or more FIFO locations are
empty.
Receive operation in mode “1”:
When the ST16C550 is in FIFO mode (FCR bit-0 =
logic 1, FCR bit-3 = logic 1) and the trigger level has
been reached, or a Receive Time Out has occurred,
the -RXRDY pin will go to a logic 0. Once activated, it
will go to a logic 1 after there are no more characters
in the FIFO.
FCR BIT 4-5: Not used.
FCR BIT 6-7: These bits are used to set the trigger level
for the receive FIFO interrupt.
An interrupt is generated when the number of characters
in the FIFO equals the programmed trigger level. How-
ever the FIFO will continue to be loaded until it is full.
BIT-7
BIT-6
RX FIFO trigger level
00
1
01
4
10
8
11
14
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ST16C550IJ44 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
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ST16C550IJ44TR-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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