參數(shù)資料
型號(hào): ST16C552CJ68-F
廠商: Exar Corporation
文件頁(yè)數(shù): 35/39頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO PAR 16B DUAL 68PLCC
標(biāo)準(zhǔn)包裝: 19
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: 打印機(jī)
電源電壓: 2.97 V ~ 5.5 V
帶并行端口:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC
包裝: 管件
其它名稱: 1016-1263-5
5
ST16C552/552A
Rev. 3.40
SYMBOL DESCRIPTION
Symbol
Pin
Signal Type
Pin Description
trailing edge of -IOR (end of the external CPU read cycle).
-IOR
37
I
Read strobe.- A logic 0 transition on this pin will place the
contents of an Internal register defined by address bits A0-
A2 for either UART channels A/B or A0-A1 for the printer
port, onto D0-D7 data bus for a read cycle by an external
CPU.
-IOW
36
I
Write strobe.- A logic 0 transition on this pin will transfer the
data on the internal data bus (D0-D7), as defined by either
address bits A0-A2 for UART channels A/B or A0-A1 for the
printer port, into an internal register during a write cycle from
an external CPU.
PD7-PD0
46-53
I/O
Printer Data port (Bi-directional three state) - These pins are
the eight bit, three state data bus for transferring information
to or from an external device (usually a printer). D0 is the
least significant bit. PD7-PD0 are latched during a write
cycle (output mode).
PE
67
I
Paper Empty - General purpose input or line printer paper
empty (Internal pull-up). This pin can be connected to
provide a printer out of paper indication.
RDOUT
44
O
Read Out (active high) - This pin goes to a logic 1 when the
external CPU is reading data from the 552/552A. This signal
can be used to enable/disable external transceivers or other
logic functions.
-RESET
39
I
Master Reset (active low) - a logic 0 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time. (See ST16C552/552A External Reset Conditions for
initialization details.)
-RXRDY A/B
9,61
O
Receive Ready A/B (active low). This function is associated
with the dual channel UARTs and provide the RX FIFO/
RHR status for individual receive channels (A-B). A logic 0
indicates there is receive data to read/unload, i.e., receive
ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is
empty or when the programmed trigger level has not been
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