REV. 5.0.3 2.90V TO 5.5V UART WITH 32-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA=0
參數(shù)資料
型號: ST16C650ACJ44-F
廠商: Exar Corporation
文件頁數(shù): 33/50頁
文件大?。?/td> 0K
描述: IC UART FIFO 32B 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點: *
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
規(guī)程: 打印機,RS232,RS422,RS485
電源電壓: 2.9 V ~ 5.5 V
帶并行端口:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱: 1016-1663
ST16C650ACJ44-F-ND
ST16C650A
39
REV. 5.0.3
2.90V TO 5.5V UART WITH 32-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.90V TO 5.5V, 70 PF LOAD
WHERE APPLICABLE
SYMBOL
PARAMETER
LIMITS
3.3V
MIN
MAX
LIMITS
5.0V
MIN
MAX
UNIT
CLK
Clock Pulse Duration
30
20
ns
OSC
Crystal Frequency
20
24
MHz
OSC
External Clock Frequency
33
50
MHz
TAS
Address Setup Time (AS# tied to GND)
5
ns
TAH
Address Hold Time (AS# tied to GND)
(top mark date code of "HC YYWW" and older)
10
ns
TAH
Address Hold Time (AS# tied to GND)
(top mark date code of "I2 YYWW" and newer)
0
ns
TCS
Chip Select Width
50
40
ns
TRD
IOR# Strobe Width
50
40
ns
TDY
Read/Write Cycle Delay
40
30
ns
TRDV
Data Access Time
40
30
ns
TDD
Data Disable Time
0
15
0
10
ns
TWR
IOW# Strobe Width
50
40
ns
TDS1
Data Setup Time (AS# tied to GND)
20
10
ns
TDH1
Data Hold Time (AS# tied to GND)
5
ns
TASW
Address Strobe Width
35
25
ns
TAS1
Address Setup Time (AS# used)
5
ns
TAH1
Address Hold Time (AS# used)
10
ns
TAS2
Address Setup Time (AS# used)
5
ns
TAH2
Address Hold Time (AS# used)
10
ns
TCS1
Delay from Chip Select to AS#
5
ns
TCSH
Delay from AS# to Chip Select
0
ns
TCS2
Delay from AS# to Chip Select
5
ns
TRD1
Delay from AS# to Read
10
ns
TRD2
Delay from Chip Select to IOR#
10
ns
TDIS
Delay from IOR# to DDIS#
15
10
ns
TWR1
Delay from AS# to IOW#
10
ns
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