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參數(shù)資料
| 型號： | ST22XJ64 |
| 英文描述： | EPROM IC; Memory Size:1Mbit; Memory Configuration:1M x 1; Package/Case:8-DIP; Supply Voltage Nom, Vcc:5V; Mounting Type:Through Hole; Voltage Rating:3.3V |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 109K |
| 代理商： | ST22XJ64 |
3/7
ST22XJ64
Figure 1
SmartJ Platform Architecture
– The ST22XJ64 has two execution modes.
Java
mode is used when JavaCard 2.1 bytecodes
are being executed.
Native
mode is used for
long JavaCard bytecodes, Native methods
and system routines. The processor enters
Java mode when a dispatch (
DISP
) instruction
is encountered. When executing in Native
mode, there are two privilege levels,
User
and
Supervisor
. Some instructions can only be exe-
cuted in
Supervisor
mode.
Instructions are of variable length, from 1 to 4
bytes in Native mode.
Special instructions exist for single-cycle stack
operations, a frequent occurrence in Java code.
Short branches and conditional branches within
a 1 KByte block or the entire 16 MByte instruc-
tion space are supported.
ST22XJ64 has four stages of pipeline in Native
mode: fetch, decode, execute and write-back.
In Java mode, there are five stages of pipeline:
bytecode-fetch, bytecode-decode, decode, ex-
ecute and write-back.
The CPU core has 16 32-bit general purpose
registers, as well as 10 special registers of var-
iable length.
– The chip also features a very high performance
Asynchronous Serial Interface (ASI) to support
high speed serial communication protocols
compatible with ISO 7816 standards.
– It is manufactured using the highly reliable ST
CMOS EEPROM technology.
EMBEDDED SOFTWARE
The Hardware Software Interface (HSI) is a set of
C interfaces to the ST22XJ64 EEPROM memory
and peripherals. The drivers are:
– EEPROM
– Asynchronous Serial Interface
– Central Interrupt Controller
– Timer
– Random Number Generator
– Clock Manager
– Memory Protection Unit
– Sensors
Important Notes:
– The HSI driver software layer is the only way to
have access to the ST22XJ64 peripherals and
EEPROM memory for programming or erasing.
– Only the OS
1)
domain can access the HSI soft-
ware layer.
ROM
EEPROM
RAM
PERIPHERALS
RAM BUS
ROM BUS
T
A
.
.
POWER MNGT.
CLOCK MNGT.
ISO
7816
S
M
R
.
SCP 160b/PRZ
32-bit
RISC
CORE
1
In the following the term OS will refer to the
software layer that is directly interfaced to
the HSI.
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