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| 型號(hào)： | ST52440G3 |
| 英文描述： | MAX 7000 CPLD 64 MC 44-TQFP |
| 中文描述： | 8位重癥監(jiān)護(hù)病房與定時(shí)器/脈寬調(diào)制。模擬比較器?？煽毓? PWM定時(shí)器。水分散粒劑。提供了8K存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 9/88頁(yè) |
| 文件大?。?/td> | 1162K |
| 代理商： | ST52440G3 |
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ST52T430/E430
17/88
The STACK POINTER indicates the first level
available to store data. When a subroutine call or
interrupt request occurs, the content of the PC and
the current set of flags are stored into the level
located by the STACK POINTER.
When a interrupt return occurs (RETI instruction),
the data stored in the highest stack level is
restored back into the PC and current flags.
Instead, when a subroutine return occurs (RET
instruction) the data stored in the highest stack
level are restored in the PC not affecting the flags.
These operating modes are illustrated in Figure
2.4.
Note:
The user must pay close attention to avoid
overwriting RAM locations where the STACK could
be stored.
2.3.2 Input Registers Bench.
The Input Registers (IR) bench consists of 20 8-bit
registers containing data or the status of the
peripherals.
All the registers can be specified by using a
decimal address (for example, 0 identifies the first
register of the IR).
The assembler instruction:
LDRI RAM_Reg. IR_i
loads the value of the i-th IR in the RAM location
identified by the RAM_Reg address.
The first input register is dedicated to store the
value of the stack pointer. The next 8 registers
(ADC_OUT_0:7) of the IR are dedicated to the 8
converted values deriving from the ADC. The last
9 Input Registers contain data from the I/O ports
and PWM/Timers. The following table summarizes
the IR address and the relative peripherals. In
order to simplify the concept, a mnemonic name is
assigned to the registers. The same name is used
in VISUALSTUDIO development tools
Figure 2.4 Stack Operation
PROGRAMCOUNTER
RAM
REG0
REG1
REG2
REG3
REG4
REG5
REG255
REG254
REG253
REG252
STACKLEVEL 1
STACKLEVEL 2
..........................
STACKLEVEL n
WHENCALL OR
INTERRUPT REQ.
WHENRETI ORRET
OCCURS
Stack
Pointer
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