參數(shù)資料
型號: ST62T18C
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 20-PIN PACKAGE
中文描述: 8位單片機(jī)與微控制器/ D轉(zhuǎn)換器,自動重加載定時器,UART的秘書長辦公室,安全復(fù)位和20管腳封裝
文件頁數(shù): 47/82頁
文件大?。?/td> 536K
代理商: ST62T18C
47/82
47
ST62T18C/E18C
AUTO-RELOAD TIMER
(Cont’d)
It should be noted that the reload values will also
affect thevalue and the resolution of the duty cycle
of PWM output signal. To obtain a signal on ARTI-
Mout, the contents of the ARCP register must be
greater than the contents of the ARRC register.
The maximum available resolution for the ARTI-
Mout duty cycle is:
Resolution = 1/[255-(ARRC)]
Where ARRCis the content of the Reload/Capture
register. The compare value loaded in the Com-
pare Register, ARCP, must be in the range from
(ARRC) to 255.
The ARTC counter is initialized by writing to the
ARRC register and by thensetting the TCLD (Tim-
er Load) and the TEN (Timer Clock Enable) bits in
the Mode Control register, ARMC.
Enabling and selection of the clock source is con-
trolled by the CC0, CC1, SL0 and SL1 bits in the
Status ControlRegister, ARSC1. The prescaler di-
vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
In Auto-reload Mode, any of the three available
clock sources can be selected: Internal Clock, In-
ternal Clock divided by 3 or the clock signal
present on the ARTIMin pin.
Figure 28. Auto-reload Timer PWM Function
COUNTER
COMPARE
VALUE
RELOAD
REGISTER
PWM OUTPUT
t
t
255
000
VR001852
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