參數(shù)資料
型號(hào)： ST6392B1
廠商： 意法半導(dǎo)體
英文描述： 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD
中文描述： 8位微控制器HCMOS電視頻率合成帶OSD
文件頁(yè)數(shù)： 22/68頁(yè)
文件大?。?/td> 560K
代理商： ST6392B1
Interrupt Vectors/Sources
The ST639x Core includes 5 different interrupt
vectors in order to branch to 5 different interrupt
routines. The interrupt vectors are located in the
fixed (or static)page of the Program Space.
The interruptvectorassociatedwith thenon-mask-
able interruptsource is named interrupt vector #0.
It is located at the (FFCh,FFDh) addresses in the
Program Space.This vector is associatedwith the
PC6/IRINpin.
The
interrupt vectors
(FF6h,FF7h),
(FF4h,FF5h),
(FF0h,FF1h) are named interrupt vectors #1, #2,
#3 and #4 respectively.These vectorsare associ-
ated with TIMER 2 (#1), VSYNC (#2), TIMER 1
(#3) andPC4(PWRIN) (#4).
Interrupt Priority
The non-maskable interrupt request has the high-
est priority and can interrupt any other interrupt
routines at any time, nevertheless the other inter-
rupts cannot interrupt each other. Ifmore than one
interrupt requestis pending,they are processedby
the ST639x Core according to their priority level:
vector #1 hasthe higherprioritywhile vector#4the
lower. The priority of eachinterrupt sourceis hard-
ware fixed.
located
at addresses
(FF2h,FF3h),
InterruptOption Register
The Interrupt Option Register (IOR register, loca-
tion C8h) is used to enable/disable the individual
interrupt sourcesand to select theoperating mode
of theexternalinterrupt inputs.Thisregistercan be
addressed in the Data Space as RAM location at
the C8h address,nevertheless it is write-only reg-
ister that can not be accessed with single-bit op-
erations. The operating modes of the external
interrupt inputs associated to interrupt vectors #1
and #2are selectedthrough bits4and 5of theIOR
register.
D7.
Not used.
EL1.
This is the Edge/Level selection bit of inter-
rupt #1.When set to one,the interruptisgenerated
on low level of the related signal; when cleared to
zero,theinterruptisgenerated onfalling edge.The
bit is cleared to zeroafter reset.
ES2.
This is the edge selectionbit on interrupt#2.
This bitisusedonthe ST639x deviceswithon-chip
OSDgenerator for VSYNCdetection.
GEN.
Thisistheglobalenablebit.Whensettooneall
interruptsareglobally enabled;whenthisbitiscleared
tozeroall interruptsaredisabled(excludingNMI).
D3 - D0.
These bits are not used.
Interrupt Source
Associated
Vector
Vector Address
PC6/IRIN
Pin
(1)
Interrupt
Vector # 0 (NMI)
0FFCh-0FFDh
Timer 2
Interrupt
Vector # 1
0FF6h-0FF7h
Vsync
Interrupt
Vector # 2
0FF4h-0FF5h
Timer 1
Interrupt
Vector # 3
0FF2h-0FF3h
PC4/PWRIN
Interrupt
Vector # 4
0FF0h-0FF1h
Note 1.
This pinis associated withtheNMI Interrupt Vector
Table 6. Interrupt Vectors/Sources
Relationships
INTERRUPT
(Continued)
IOR
InterruptOption Register
(C8h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Unused
GEN =GlobalEnable Bit
ES2 =Edge SelectionBit
EL1 = EdgeLevelSelection Bit
Unused
Figure 20. InterruptOption Register
ST6391,92,93,95,97,99
18/64
相關(guān)PDF資料
PDF描述
ST6393B1 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD
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