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參數(shù)資料
| 型號： | ST6393B1 |
| 廠商： | 意法半導體 |
| 英文描述： | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| 中文描述： | 8位微控制器HCMOS電視頻率合成帶OSD |
| 文件頁數(shù)： | 46/68頁 |
| 文件大?。?/td> | 560K |
| 代理商： | ST6393B1 |
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D7-D5.
These bits arenot used.
VSYNC.
This bit reads the status of the VSYNC
pin. Itis inverted with respectto the pin.
IR.
This bit reads the status of the IRlatch. Ifa sig-
nal hasbeen latched thisbit will be high.
AD2-AD0.
These bits store the real time conver-
sion ofthe value present onthe AFC input pin.Un-
defined reset value.
D7, D6, D5, D4, D3, D1, D0.
These bits are not
used.
A/D Shift.
Thisbit determinesthe voltage rangeof
the AFCinput. Writing azerowill select the 0.5Vto
4.5V range. Writing a one will select the 1.0V to
5.0V range.Undefined afterreset.
AFCR
AFC Result Register
(E4h, Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
AD2-AD0 A/D= Conv Result
IR
VSYNC
Unused
Figure53. AFC,IR and OSD Result Register
AFSR
AFC Shift Register
(E5h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Unused
A/D Shift Bit
Unused
Figure54. Outputs Control Register
AFC A/D COMPARATOR
(Continued)
DEDICATED LATCHES
Two latches are available which may generate in-
terrupts to the ST639x core. The IR latch is set
either by the falling or rising edge ofthe signal on
pin PC6(IRIN). Ifbit 1(IRPOSEDGE)of thelatches
register (E9h) is high, then the latch will be trig-
gered onthe risingedge ofthesignalat PC6(IRIN).
If bit 1 (IRPOSEDGE)is low, then the latch will be
triggered on the falling edge of the signal at
PC6(IRIN). The IR latch can be reset by settingbit
3 (RESIRLAT)of the latches register; the bit is set
only anda highshould bewritteneverytime theIR
latch needs to be reset. If bit 2 (IRINTEN) of the
latchesregister(E9h) ishigh,thentheoutputofthe
IR latch, IRINTN, may generate an interrupt (#0).
IRINTN is inverted with respect to the stateof the
IR latch.Ifbit2(IRINTEN) is low, then theoutputof
the IR latch, IRINTN, is forced high. The state of
the IR latch may be read from bit 3 (IRLATCH)of
register E4h;if the IR latch is set,then bit3 will be
high. The PWR latch is set either by the falling or
rising edge of the signal on pin PC4(PWRIN).If bit
4 (PWREDGE)ofthe latches register(E9h)is high,
then thelatch will be triggeredon therising edge of
the signal at PC4(PWRIN). If bit 4 (PWREDGE) is
low, then the latch will be triggered on the falling
edge ofthesignal at PC4(PWRIN).The PWRlatch
can be reset by setting bit 6 (RESPWRLAT) of the
latches register; the bit is set only and a high
should be written every time the PWR latch needs
to be reset. If bit5 (PWRINTEN) of thelatches reg-
ister (E9h) is high, then the output of the PWR
latch, PWRINTN, may generate an interrupt (#4).
PWRINTN is inverted with respect to the state of
the PWR latch. If bit 5 (PWRINTEN) is low, then
the output of the PWR latch, PWRINTN, is forced
high.
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