參數(shù)資料
型號(hào): ST70134A
英文描述: ASCOT (TM) INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
中文描述: 阿斯科特(TM)集成寬頻CMOS模擬前端電路
文件頁(yè)數(shù): 15/22頁(yè)
文件大?。?/td> 154K
代理商: ST70134A
ST70134A
15/22
Control Interface Timing
The word clock (CLWD) is used to sample at negative going edge the control information. The start bit
b15 is transmitted first followed by bits b[14:0] and at least 16 stop bits need to be provided to validate the
data.
Figure 8 :
Control Interface
Data set-up and hold time versus falling edge CLWD must be greater than 10nsec.
Receive / Transmit Interface
RECEIVE / TRANSMIT PROTOCOL
The digital interface is based on 4 x 8.832MHz (35.328MHz) data lines in the following manner:
If OSR = 2 (OSR bit set to 1) is selected, CLKNIB is used as nibble clock (17.664MHz, disabled in normal
mode), and all the RXi, TXi, CLKWD periods are twice as long as in normal mode. This ensures a
compatibility with lower speed products.
TX Signal Dynamic
The dynamic of data signal for both TX DACs is 12 bits extracted from the available signed 16 bit repre-
sentation coming from the digital processor.
The maximal positive number is 2
14
-1, the most negative number is -2
14
, the 3 LSBs are filled with ’0’.
Any signal exceeding these limits is clamped to the maximum value.
Table 18 :
TX Data Bit Map
The two sign bits must be identical.
BIT MAP/NIBBLE
N0
N1
N2
N3
TXD0
not used
data bit 1
data bit 5
data bit 9
TXD1
not used
data bit 2
data bit 6
data bit 10
TXD2
not used
data bit 3
data bit 7
data SIGN
TXD3
d0 = data bit 0 (LSB)
data bit 4
data bit 8
data SIGN
Table 19 :
TX Nibble Bit Map
N3
N2
N1
N0
sign
sign
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
n.u.
n.u.
n.u.
Data
ID.
CLWD
CTRLIN
Start
Bit
>=16 Stop
Bits = High
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