參數(shù)資料
型號(hào)： ST70136G
廠商： 意法半導(dǎo)體
英文描述： CPE ADSL ANALOG FRONT END
中文描述： 終端ADSL模擬前端
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 361K
代理商： ST70136G
ST70136
10/24
Figure 4 :
Control Register Interface Read cycle
4.7.1 - AFE registers
4.7.1.1 - Rx Gain Control
This register is located at the address “000” and is used to program the gain in the receive path.
4.7.1.2 - Tx Gain Control
This register is located at the address “001” and is used to program the gain in the transmit path.
Table 2 :
Rx Gain Control (address [b2:b0]=”000”)
Name
Pos.
Type
Def.
Description
GC[1:0]
14.13
R/W
00
bit14: selects External Gain Control
GC1
bit13: selects External Gain control
GC0
Other
12
R/W
0
Reserved
RxAGC
11..7
R/W
00000
Select internal gain for Receive amplifier
00000 : 0dB
11111 : 31dB
RxAtt
6..5
R/W
00
Receive attenuator
00 = 0dB
01 = -4dB
10 = -8dB
11 = -12dB
Other
4.3
R/W
00
Reserved
Table 3 :
Tx Gain Control (address [b2:b0]=”001”)
Name
Pos.
Type
Def.
Description
TxAGC
14..11
R/W
0000
Select internal gain for Transmit amplifier
0000 : -15dB
1111 : 0dB
Other
10..3
R/W
0..0
Reserved
CLKM
CLKWD
Don’t care
[b2:b0]
CTRLIN
Data [b14:b3]
CTRLOUT
R/NW
b15
b15
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