參數(shù)資料
型號： ST72324BLJ2TA/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, TQFP-44
文件頁數(shù)： 29/151頁
文件大?。?/td> 1209K
代理商： ST72324BLJ2TA/XXX
ST72F324L, ST72324BL
124/151
12.8 I/O PORT PIN CHARACTERISTICS
12.8.1 General Characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be
respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD
while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the
corresponding VIN maximum must always be respected
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 64). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 65).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 64. Connecting Unused I/O Pins
Figure 65. Typical IPU vs. VDD with VIN=VSS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage 1)
0.3xVDD
V
VIH
Input high level voltage 1)
0.7xVDD
V
Vhys
Schmitt trigger voltage hysteresis 2)
0.8
IINJ(PIN)
3)
Injected Current on flash device pin
PB0
0+4
mA
Injected Current on other I/O pins
± 4
mA
ΣI
INJ(PIN)
3) Total injected current (sum of all I/O
and control pins)
VDD=3V
± 25
Ilkg
Input leakage current
VSS ≤ VIN ≤ VDD
±1
A
IS
Static current consumption
Floating input mode4)
200
RPU
Weak pull-up equivalent resistor 5)
VIN=VSS
VDD=3V
110
180
250
k
CIO
I/O pin capacitance
5
pF
tf(IO)out
Output high to low level fall time 1)
CL=50pF
Between 10% and 90%
25
ns
tr(IO)out
Output low to high level rise time 1)
25
tw(IT)in
External interrupt pulse time 6)
1tCPU
10k
UNUSED I/O PORT
ST72XXX
10k
UNUSED I/O PORT
ST72XXX
VDD
0
10
20
30
40
50
60
70
80
90
22.5
33.5
4
4.5
55.5
6
Vdd(V)
Ipu(
u
A
)
Ta=1 40°C
Ta=9 5°C
Ta=2 5°C
Ta=-45 °C
1
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