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參數(shù)資料
| 型號(hào)： | ST72344S2T6TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, TQFP-32 |
| 文件頁(yè)數(shù)： | 45/246頁(yè) |
| 文件大小： | 2016K |
| 代理商： | ST72344S2T6TR |
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ST72344xx, ST72345xx
On-chip peripherals
139/246
Setting the RWU bit by software puts the SCI in sleep mode:
●
None of the reception status bits can be set.
●
All the receive interrupts are inhibited.
A muted receiver can be woken up in one of the following two ways:
●
by Idle Line detection if the WAKE bit is reset,
●
by Address Mark detection if the WAKE bit is set.
A receiver wakes-up by Idle Line detection when the Receive line has recognized an Idle
Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.
A receiver wakes-up by Address Mark detection when it received a “1” as the most
significant bit of a word, thus indicating that the message is an address. The reception of
this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which
allows the receiver to receive this word normally and to use it as an address word.
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 55.
Note:
In case of wakeup by an address mark, the MSB bit of the data is taken into account and not
the parity bit
Even parity: The parity bit is calculated to obtain an even number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain an odd number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data
register is not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte
has an even number of “1s” if even parity is selected (PS = 0) or an odd number of “1s” if
odd parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR
register and an interrupt is generated if PIE is set in the SCICR1 register.
Table 55.
Frame formats
M bit
PCE bit
SCI frame(1)
1.
SB: Start Bit, STB: Stop Bit, PB: Parity Bit.
0
| SB | 8 bit data | STB |
1
| SB | 7-bit data | PB | STB |
1
0
| SB | 9-bit data | STB |
1
| SB | 8-bit data PB | STB |
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72344S4T6 | MICROCONTROLLER, PQFP44 |
| ST72345C4T6TR | MICROCONTROLLER, PQFP48 |
| ST72521AR7T1/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| ST72521R7T5/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| ST72521AR7TC/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72345 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8-BIT MCU WITH UP TO 16K FLASH MEMORY, 10-BIT ADC, TWO 16-BIT TIMERS, TWO I2C, SPI, SCI |
| ST72345-D/RAIS | 功能描述:子卡和OEM板 8 BITS MICROCONTR RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| ST72361 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8-bit MCU with Flash or ROM, 10-bit ADC, 5 timers, SPI, 2x LINSCI⑩ |
| ST72361_07 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8-bit MCU with Flash or ROM, 10-bit ADC, 5 timers, SPI, 2x LINSCI⑩ |
| ST72361K6T6 | 制造商:STMicroelectronics 功能描述:ROMLESS MICRO WITH 2 UART - Bulk |
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