參數(shù)資料
型號(hào)： ST72521AR7TC/XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, PLASTIC, TQFP-64
文件頁數(shù)： 33/199頁
文件大?。?/td> 1979K
代理商： ST72521AR7TC/XXX
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ST72521M/R/AR
128/199
CONTROLLER AREA NETWORK (Cont’d)
10.8.2 Main Features
– Support of CAN specification 2.0A and 2.0B pas-
sive
– Three prioritized 10-byte Transmit/Receive mes-
sage buffers
– Two programmable global 12-bit message ac-
ceptance filters
– Programmable baud rates up to 1 MBit/s
– Buffer flip-flopping capability in transmission
– Maskable interrupts for transmit, receive (one
per buffer), error and wake-up
– Automatic low-power mode after 20 recessive
bits or on demand (standby mode)
– Interrupt-driven wake-up from standby mode
upon reception of dominant pulse
– Optional dominant pulse transmission on leaving
standby mode
– Automatic message queuing for transmission
upon writing of data byte 7
– Programmable loop-back mode for self-test op-
eration
– Advanced error detection and diagnosis func-
tions
– Software-efficient buffer mapping at a unique ad-
dress space
– Scalable architecture.
10.8.3 Functional Description
10.8.3.1 Frame Formats
A summary of all the CAN frame formats is given
in Figure 68 for reference. It covers only the stand-
ard frame format since the extended one is only
acknowledged.
A message begins with a start bit called Start Of
Frame (SOF). This bit is followed by the arbitration
field which contains the 11-bit identifier (ID) and
the Remote Transmission Request bit (RTR). The
RTR bit indicates whether it is a data frame or a re-
mote request frame. A remote request frame does
not have any data byte.
The control field contains the Identifier Extension
bit (IDE), which indicates standard or extended
format, a reserved bit (ro) and, in the last four bits,
a count of the data bytes (DLC). The data field
ranges from zero to eight bytes and is followed by
the Cyclic Redundancy Check (CRC) used as a
frame integrity check for detecting bit errors.
The acknowledgement (ACK) field comprises the
ACK slot and the ACK delimiter. The bit in the ACK
slot is placed on the bus by the transmitter as a re-
cessive bit (logical 1). It is overwritten as a domi-
nant bit (logical 0) by those receivers which have
at this time received the data correctly. In this way,
the transmitting node can be assured that at least
one receiver has correctly received its message.
Note that messages are acknowledged by the re-
ceivers regardless of the outcome of the accept-
ance test.
The end of the message is indicated by the End Of
Frame (EOF). The intermission field defines the
minimum number of bit periods separating con-
secutive messages. If there is no subsequent bus
access by any station, the bus remains idle.
10.8.3.2 Hardware Blocks
The CAN controller contains the following func-
tional blocks (refer to Figure 67):
– ST7 Interface: buffering of the ST7 internal bus
and address decoding of the CAN registers.
– TX/RX Buffers: three 10-byte buffers for trans-
mission and reception of maximum length mes-
sages.
– ID Filters: two 12-bit compare and don’t care
masks for message acceptance filtering.
– PSR: page selection register (see memory map).
– BRPR: clock divider for different data rates.
– BTR: bit timing register.
– ICR: interrupt control register.
– ISR: interrupt status register.
– CSR: general purpose control/status register.
– TECR: transmit error counter register.
– RECR: receive error counter register.
– BTL: bit timing logic providing programmable bit
sampling and bit clock generation for synchroni-
zation of the controller.
– BCDL: bit coding logic generating a NRZ-coded
datastream with stuff bits.
– SHREG: 8-bit shift register for serialization of
data to be transmitted and parallelisation of re-
ceived data.
– CRC: 15-bit CRC calculator and checker.
– EML: error detection and management logic.
– CAN Core: CAN 2.0B passive protocol control-
ler.
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