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| 型號(hào)： | ST72651AR6T1E/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, TQFP-64 |
| 文件頁(yè)數(shù)： | 92/161頁(yè) |
| 文件大?。?/td> | 2656K |
| 代理商： | ST72651AR6T1E/XXX |
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ST72651AR6
36/161
Doc ID 7215 Rev 4
POWER SUPPLY MANAGEMENT (Cont’d)
6.4.4 Register Description
POWER CONTROL REGISTER (PCR)
Reset Value: 0000 0000 (00h)
Bit 7 = ITPF Voltage Input Threshold Plus Flag
This bit is set by hardware when USBVDD rises
over USBVIT+ and cleared by hardware when US-
BVDD drops below USBVIT+.
0: USBVDD < USBVIT+
1:USBVDD > USBVIT+
Bit 6 = ITMF Voltage Input Threshold Minus Flag
This bit is set by hardware when USBVDD rises
over USBVIT- and cleared by hardware when US-
BVDD drops below USBVIT-.
0: USBVDD < USBVIT-
1:USBVDD > USBVIT-
Bit 5 = PLG USB Plug/Unplug detection.
This bit is set by hardware when it detects that the
USB cable has been plugged in. It is cleared by
hardware when the USB cable is unplugged. (De-
tection happens when USBVDD rises over USB-
VIT+ or when USBVDD drops below USBVIT-). If
the PLGIE bit is set, the rising/falling edge of the
PLG bit also generates an interrupt request. This
interrupt is able to wake up the ST7 core from Halt
mode.
0: USB cable unplugged
1: USB cable plugged in
Bit 4 = PLGIE USB Plug/Unplug Interrupt Enable.
This bit is set and cleared by software.
0: Single supply mode: PLG interrupt disabled.
1: Dual supply mode: PLG interrupt enabled (gen-
erates an interrupt on the rising/falling edge of
PLG).
Bit 3:2 = VSET[1:0] Voltage Regulator Output
Voltage.
These bits are set and cleared by software to se-
lect the output voltage of the on-chip voltage regu-
lator (for the VDDF output).
Bit 1 = DETEN USB Voltage Detector Enable.
This bit is set and cleared by software. It is used to
power-off the USB voltage detector in Stand-alone
mode to reduce unnecessary power consumption,
especially in HALT mode.
0: The USB voltage detector is enabled.
1: The USB voltage detector disabled (ITPF, ITMF
and PLG bits are forced high)
Bit 0 = REGEN Voltage Regulator Enable.
This bit is set and cleared by software.
0: The regulator is completely shutdown and no
current is drawn from the power supply by the
voltage reference.
1: The on-chip voltage regulator is powered-on.
Related Documentation
AN1529: Extending the current & voltage capabili-
ty on the ST7265 VDDF Supply
70
ITPF
ITM
F
PLG
IE
VSE
T1
VSE
T0
DET
EN
REG
EN
VSE
T1
VSE
T0
Voltage output of the regulator
0
3.5V
0
1
3.4V
1
0
3.3V
1
2.8V
1
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