參數(shù)資料
型號(hào)： ST72F324J2B6
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, PLASTIC, SDIP-42
文件頁數(shù)： 152/156頁
文件大?。?/td> 1027K
代理商： ST72F324J2B6
ST72324J/K
95/156
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.4.7 Parity Control
Parity control (generation of parity bit in trasmis-
sion and and parity chencking in reception) can be
enabled by setting the PCE bit in the SCICR1 reg-
ister. Depending on the frame length defined by
the M bit, the possible SCI frame formats are as
listed in Table 20.
Table 20. Frame Formats
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Note: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
Even parity: the parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an
odd number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is se-
lected (PS=1). If the parity check fails, the PE flag
is set in the SCISR register and an interrupt is gen-
erated if PIE is set in the SCICR1 register.
10.5.5 Low Power Modes
10.5.6 Interrupts
The SCI interrupt events are connected to the
same interrupt vector.
These events generate an interrupt if the corre-
sponding Enable Control Bit is set and the inter-
rupt mask in the CC register is reset (RIM instruc-
tion).
M bit
PCE bit
SCI frame
0
| SB | 8 bit data | STB |
0
1
| SB | 7-bit data | PB | STB |
1
0
| SB | 9-bit data | STB |
1
| SB | 8-bit data PB | STB |
Mode
Description
WAIT
No effect on SCI.
SCI interrupts cause the device to exit
from Wait mode.
HALT
SCI registers are frozen.
In Halt mode, the SCI stops transmit-
ting/receiving until Halt mode is exit-
ed.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Transmit Data Register
Empty
TDRE
TIE
Yes
No
Transmission Com-
plete
TC
TCIE
Yes
No
Received Data Ready
to be Read
RDRF
RIE
Yes
No
Overrun Error Detected
OR
Yes
No
Idle Line Detected
IDLE
ILIE
Yes
No
Parity Error
PE
PIE
Yes
No
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ST72F324J2T6TR 功能描述:8位微控制器 -MCU 5V RANGE 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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ST72F324J2TAE 功能描述:8位微控制器 -MCU 5V RANGE 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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