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參數(shù)資料
| 型號： | ST72F340S2T6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, LEAD FREE, LQFP-44 |
| 文件頁數(shù)： | 44/191頁 |
| 文件大?。?/td> | 3285K |
| 代理商： | ST72F340S2T6 |
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ST72340, ST72344, ST72345
138/191
I2C3S INTERFACE (Cont’d)
Bit 3= WP1 Write Protect enable for Slave 1
This bit is set and cleared by software. It is also
cleared by hardware when the interface is disa-
bled (PE=0).
0: Write access to Slave 1 RAM buffer enabled
1: Write access to Slave 1 RAM buffer disabled
Notes: (Applicable for both WP2/ WP1)
– Only write operations are disabled/enabled.
Read operations are not affected.
– If a write operation is attempted, the slave ad-
dress is acknowledged, the current address reg-
ister is overwritten, data is also acknowledged
but it is not written to the RAM.
– Both the current address and byte count regis-
ters are incremented as in normal operation.
– No interrupt generated if slave is write protected
– BusyW will not be set if slave is write protected
Bit 2= PE Peripheral enable
This bit is set and cleared by software.
0: Peripheral disabled
1: Slave capability enabled
Note: To enable the I2C interface, write the CR
register TWICE with PE=1 as the first write only
activates the interface (only PE is set)
Bit 1 = BusyW Busy on Write to RAM Buffer
This bit is set by hardware when a STOP/ RE-
START is detected after a write operation. The
I2C3S peripheral is temporarily disabled till this bit
is reset. This bit is cleared by software. If this bit is
not cleared before the next slave address recep-
tion, further communication will be non-acknowl-
edged. This bit is set to 1 when modifying any bits
in Control Register 2. Writing a 1 to this bit does
not actually modify BusyW but prevents acciden-
tally clearing of the bit.
0: No BusyW event occurred
1: A STOP/ RESTART is detected after a write op-
eration
Bit 0 = B/W Byte / Word Mode
This control bit must be set by software before a
word is updated in the RAM buffer and cleared by
hardware after completion of the word update. In
Word mode the CPU cannot be interrupted when it
is modifying the LSB byte and MSB byte of the
word. This mode is to ensure the coherency of
data stored as words.
0: Byte mode
1: Word mode
Note: When word mode is enabled, all interrupts
should be masked while the word is being written
in RAM.
I2C3S STATUS REGISTER (I2C3SSR)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7= NACK Non Acknowledge not followed by
Stop
This bit is set by hardware when a non acknowl-
edge returned by the master is not followed by a
Stop or Restart condition. It is cleared by software
reading the SR register or by hardware when the
interface is disabled (PE=0).
0: No NACK error occurred
1: Non Acknowledge not followed by Stop
Bit 6 = BERR Bus error
This bit is set by hardware when the interface de-
tects a misplaced Start or Stop condition. It is
cleared by software reading SR register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Bit 5 = WF3 Write operation to Slave 3
This bit is set by hardware on reception of the di-
rection bit in the I2C address byte for Slave 3. This
bit is cleared when the status register is read when
there is no communication ongoing or when the
peripheral is disabled (PE = 0)
0: No write operation to Slave 3
1: Write operation performed to Slave 3
Bit 4 = WF2 Write operation to Slave 2
This bit is set by hardware on reception of the di-
rection bit in the I2C address byte for Slave 2. This
bit is cleared when the status register is read when
there is no communication ongoing or when the
peripheral is disabled (PE = 0)
0: No write operation to Slave 2
1: Write operation performed to Slave 2
Bit 3 = WF1 Write operation to Slave 1
This bit is set by hardware on reception of the di-
rection bit in the I2C address byte for Slave 1. This
bit is cleared by software when the status register
is read when there is no communication ongoing
70
NACK BERR
WF3
WF2
WF1
RF3
RF2
RF1
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ST72F340S4T6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST72F344K2T6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST72F344K4T6 | 功能描述:8位微控制器 -MCU 8-BIT MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST72F344K4T6TR | 功能描述:8位微控制器 -MCU 8-bit MCU 16 Flash Memore RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| ST72F344S2T6 | 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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