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參數(shù)資料
| 型號： | ST72F345N4H6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PBGA56 |
| 封裝： | 6 X 6 MM, LEAD FREE, TFBGA-56 |
| 文件頁數(shù)： | 37/190頁 |
| 文件大?。?/td> | 3666K |
| 代理商： | ST72F345N4H6 |
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ST72340, ST72344, ST72345
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I2C3S INTERFACE (Cont’d)
11.7.4 Functional Description
The three slave addresses 1, 2 and 3 can be used
as general purpose I2C slaves. They also support
all features of standard I2C EEPROMs like the ST
M24Cxx family and are able to fully emulate them.
Slaves 1 and 2 are mapped on the same interrupt
vector. Slave 3 has a separate interrupt vector with
higher priority.
The three slave addresses are defined by writing
the 7 MSBs of the address in the I2C3SSAR1,
I2C3SSAR2
and
I2C3SSAR3
registers.
The
slaves are enabled by setting the enable bits in the
same registers.
Each slave has its own RAM buffer at a fixed loca-
tion in the ST7 RAM area.
– Slaves 1 and 2 have 256-byte buffers which can
be individually protected from I2C master write
accesses.
– Slave 3 has a 128-byte RAM buffer without write
protection feature.
All three slaves have individual read flags (RF)
and write flags (WF) with maskable interrupts.
These flags are set when the I2C master has com-
pleted a read or write operation.
11.7.4.1 Paged operation
To allow emulation of Standard I2C EEPROM de-
vices, pages can be defined in the RAM buffer.
The pages are configured using the PL[1:0] bits in
the I2C3SCR1 register. 8/16-Byte page length has
to be selected depending on the EEPROM device
to emulate. The Full Page option is to be used
when no paging of the RAM buffer is required. The
configuration is common to the 3 slave addresses.
The Full Page configuration corresponds to 256
bytes for address 1 and 2 and to 128 bytes for ad-
dress 3.
Paging affects the handling of rollover when write
operations are performed. In case the bottom of
the page is reached, the write continues from the
first address of the same page. Page length does
not affect read operations: rollover is done on the
whole RAM buffer whatever the configured page
length.
The Byte count register is reset when it reaches
256 bytes, whatever the page length, for all slave
addresses, including slave 3.
11.7.4.2 DMA
The I2C slaves use a DMA controller to write/read
data to/from their RAM buffer.
A DMA request is issued to the DMA controller on
reception of a byte or just before transmission of a
byte.
When a byte is written by DMA in RAM, the CPU is
stalled for max. 2 cycles. When several bytes are
transferred from the I2C bus to RAM, the DMA re-
leases between each byte and the CPU resumes
processing until the DMA writes the next byte.
11.7.4.3 RAM Buffer Write Protection
By setting the WP1/WP2 bits in the I2C3SCR2
register it is possible to protect the RAM buffer of
Slaves 1/2 respectively against write access from
the master.
If a write operation is attempted, the slave address
is acknowledged, the current address register is
overwritten, data is also acknowledged but it is not
written to the RAM. Both the current address and
byte count registers are incremented as in normal
operation.
In case of write access to a write protected ad-
dress, no interrupt is generated and the BusyW bit
in the I2C3SCR2 register is not set.
Only write operations are disabled/enabled. Read
operations are not affected.
11.7.4.4 Byte-pair coherency for I2C Read
operations
Byte-pair coherency allows the I2C master to read
a 16-bit word and ensures that it is not corrupted
by a simultaneous CPU update. Two mechanisms
are implemented, covering the two possible cases:
1. CPU updates a word in RAM after the first byte
has been transferred to the I2C shift register
from RAM. In this case, the first byte read from
RAM would be the MSB of the old word and
2nd byte would be the LSB of the new word.
To prevent this corruption, the I2C3S uses
DMA to systematically read a 2-byte word when
it receives a read command from the I2C mas-
ter. The MSB of the word should be at address
2n. Using DMA, the MSB is moved from RAM
address 2n to the I2C shift register and the LSB
from RAM address 2n+1 moved to a shadow
register in the I2C3S peripheral. The CPU is
stalled for a maximum of 2 cycles during word
transfer.
In case only one byte is read, the unused con-
tent of the shadow register will be automatically
overwritten when a new read operation is per-
formed.
In case a second byte is read in the same I2C
message (no Stop or Restart condition) the
content of the shadow register is transferred to
the shift register and transmitted to the master.
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| ST72F361AR6T3 | 功能描述:8位微控制器 -MCU 8B MCU with Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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| ST72F361AR6TA | 功能描述:8位微控制器 -MCU 8-bit MCU Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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