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參數(shù)資料
| 型號(hào)： | ST72F651AR6T1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, ROHS COMPLIANT, TQFP-64 |
| 文件頁(yè)數(shù)： | 123/161頁(yè) |
| 文件大?。?/td> | 2656K |
| 代理商： | ST72F651AR6T1 |
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ST72651AR6
64/161
Doc ID 7215 Rev 4
USB INTERFACE (Cont’d)
11.3.4 USB Data Buffer Manager
The USB Data Buffer Manager performs the data
transfer between the USB interface and the two
512 Bytes RAM areas used for Endpoint 2 in both
Upload and Download modes. It also controls the
status of Endpoint 2, by setting the endpoint as
NAK when the current buffer is not yet available for
either transmission (Upload) or reception (Down-
load).
It is based on a stand-alone hardware state-ma-
chine that runs in parallel to the ST7 processing
flow. However, at any time, the ST7 software can
initialize the USB Data Buffer Manager state-ma-
chine in order to synchronize operations by writing
a ‘1’ to the CLR bit in the BUFCSR register.
Dedicated buffer status flags are defined to syn-
chronize the USB Data Buffer Manager with the
Data Transfer Coprocessor (DTC). These flags
are used by the software plug-ins provided by ST-
Microelectronics) running on the DTC.
11.3.4.1 Data Transfer Modes
In USB normal mode (MOD[1:0]=00b), the maxi-
mum memory size of Endpoint 2 is 64 bytes, and
therefore reception of 512 bytes packets requires
ST7 software intervention every 64 bytes. This
means that after a CTR interrupt the hardware
puts the Endpoint 2 status bits for the current di-
rection (transmit or receive) in NAK status. The
ST7 software must then write the status bits to
VALID when it is ready to transmit or receive new
data.
On the contrary, in Upload or Download mode, the
physical address of Endpoint 2 is automatically in-
cremented every 64 bytes until a 512-byte buffer is
full.
Toggling between the two buffers is automatically
managed as soon as 512 bytes have been trans-
mitted to USB (Upload mode) or received from
USB (Download), if the next buffer is available:
Otherwise, the endpoint is set to invalid until a
buffer has been released by the DTC.
11.3.4.2 Switching back to Normal Mode
The USB interface is reset by hardware in Normal
mode on reception of a packet with a length below
the maximum packet size. In this case, the few
bytes are received into one of the two 512-byte
buffers and the ST7 must process by software the
data received. For this purpose, the information in-
dicating which 512-byte buffer was last addressed
is given to the ST7 by the USB Data Buffer Manag-
er (BUFNUM bit in the BUFCSR register), and the
number of received bytes is obtained by reading
the USB interface registers. With these two items
of information, the ST7 can determine what kind of
data has been received, and what action has to be
taken.
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72F651AR6T1E | 功能描述:8位微控制器 -MCU Flash 32K USB/DTC/I2 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72P262M6/OZXTR | 制造商:STMicroelectronics 功能描述:ST72P262M6/OZXTR |
| ST72P324TA/OBZTR | 制造商:STMicroelectronics 功能描述: |
| ST72P324TA/OHXTR | 制造商:STMicroelectronics 功能描述: |
| ST72P4T128M-A05AU | 制造商:STEC Inc 功能描述:1GB,ECC,REG,DDR2-400,UNLEAD - Bulk |
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