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| 型號(hào)： | ST7LITE10F1M6 |
| 英文描述： | FUSE PULLER/TESTERFUSE PULLER/TESTER; Depth, external:15mm; Length:60mm; Voltage rating, AC:24V; Voltage rating, DC:24V; Width, external:20mm |
| 中文描述： | ST7LITE1 - 8單電壓閃存EEPROM的MEMORY.DATA位MCU。 ADC的。 4定時(shí)器。的SPI |
| 文件頁(yè)數(shù)： | 38/122頁(yè) |
| 文件大?。?/td> | 1716K |
| 代理商： | ST7LITE10F1M6 |
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ST7LITE0, ST7SUPERLITE
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1
POWER SAVING MODES
(Cont’d)
9.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the LTCSR/ATCSR reg-
ister status as shown in the following table:.
9.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when active halt mode is enabled.
The MCU can exit ACTIVE-HALT mode on recep-
tion of a Lite Timer / AT Timer interrupt or a RE-
SET.
– When exiting ACTIVE-HALT mode by means of
a RESET, a 256 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation
by fetching the reset vector which woke it up (see
Figure 25
).
– When exiting ACTIVE-HALT mode by means of
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see
Figure 25
).
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
Caution:
As soon as ACTIVE-HALT is enabled,
executing a HALT instruction while the Watchdog
is active does not generate a RESET if the
WDGHALT bit is reset.
This means that the device cannot spend more
than a defined delay in this power saving mode.
Figure 24. ACTIVE-HALT Timing Overview
Figure 25. ACTIVE-HALT Mode Flow-chart
Notes:
1.
This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2.
Peripherals clocked with an external clock
source can still be active.
3.
Only the Lite Timer RTC and AT Timer interrupts
can exit the MCU from ACTIVE-HALT mode.
4.
Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
LTCSR
TBIE bit
ATCSR
OVFIE
bit
ATCSR
CK1 bit
ATCSR
CK0 bit
Meaning
0
0
0
1
x
x
0
1
x
1
x
x
1
x
0
0
x
1
x
1
ACTIVE-HALT
mode disabled
ACTIVE-HALT
mode enabled
HALT
RUN
RUN
256 CPU
CYCLE DELAY
1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[Active Halt Enabled]
FETCH
VECTOR
ACTIVE
HALT
INSTRUCTION
(Active Halt enabled)
RESET
INTERRUPT
3)
Y
N
N
Y
CPU
I BIT
OSCILLATOR
PERIPHERALS
2)
ON
OFF
OFF
0
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
I BIT
OSCILLATOR
PERIPHERALS
2)
ON
OFF
ON
X
4)
CPU
I BITS
OSCILLATOR
PERIPHERALS
ON
ON
ON
X
4)
256 CPU CLOCK CYCLE
DELAY
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