- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98147 > ST92F120JV1T (STMICROELECTRONICS) 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | ST92F120JV1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 13/313頁 |
| 文件大?。?/td> | 4439K |
| 代理商： | ST92F120JV1T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁第279頁第280頁第281頁第282頁第283頁第284頁第285頁第286頁第287頁第288頁第289頁第290頁第291頁第292頁第293頁第294頁第295頁第296頁第297頁第298頁第299頁第300頁第301頁第302頁第303頁第304頁第305頁第306頁第307頁第308頁第309頁第310頁第311頁第312頁第313頁
11/313
ST92F120 - GENERAL INFORMATION
Figure 3. CMOS basic inverter
When an input is kept at logic zero, the N-channel
transistor is off, while the P-channel is on and can
conduct. The opposite occurs when an input is
kept at logic one. CMOS transistors are essentially
linear devices with relatively broad switching
points. During commutation, the input passes
through midsupply, and there is a region of input
voltage values where both P and N-channel tran-
sistors are on. Since normally the transitions are
fast, there is a very short time in which a current
can flow: once the switching is completed there is
no longer current. This phenomenon explains why
the overall current depends on the switching rate:
the consumption is directly proportional to the
number of transistors inside the device which are
in the linear region during transitions, charging and
discharging internal capacitances.
In order to avoid extra power supply current, it is
important to bias input pins properly when not
used. In fact, if the input impedance is very high,
pins can float, when not connected, either to a
midsupply level or can oscillate (injecting noise in
the device).
Depending on the specific configuration of each
I/O pin on different ST9 devices, it can be more or
less critical to leave unused pins floating. For this
reason, on most pins, the configuration after RE-
SET enables an internal weak pull-up transistor in
order to avoid floating conditions. For other pins
this is intrinsically forbidden, like for the true open-
drain pins. In any case, the application software
must program the right state for unused pins to
avoid conflicts with external circuitry (whichever it
is: pull-up, pull-down, floating, etc.).
The suggested method of terminating unused I/O
is to connect an external individual pull-up or pull-
down for each pin, even though initialization soft-
ware can force outputs to a specified and defined
value, during a particular phase of the RESET rou-
tine there could be an undetermined status at the
input section.
Usage of pull-ups and/or pull-downs is preferable
in place of direct connection to VDD or VSS. If pull-
up or pull-down resistors are used, inputs can be
forced for test purposes to a different value, and
outputs can be programmed to both digital levels
without generating high current drain due to the
conflict.
Anyway, during system verification flow, attention
must be paid to reviewing the connection of each
pin, in order to avoid potential problems.
1.2.4 Avoidance of Pin Damage
Although integrated circuit data sheets provide the
user with conservative limits and conditions in or-
der to prevent damage, sometimes it is useful for
the hardware system designer to know the internal
failure mechanisms: the risk of exposure to illegal
voltages and conditions can be reduced by smart
protection design.
It is not possible to classify and to predict all the
possible damage resulting from violating maxi-
mum ratings and conditions, due to the large
number of variables that come into play in defining
the failures: in fact, when an overvoltage condition
is applied, the effects on the device can vary sig-
nificantly depending on lot-to-lot process varia-
tions, operating temperature, external interfacing
of the ST9 with other devices, etc.
In the following sections, background technical in-
formation is given in order to help system design-
ers to reduce risk of damage to the ST9 device.
1.2.4.1 Electrostatic Discharge and Latchup
CMOS integrated circuits are generally sensitive
to exposure to high voltage static electricity, which
can induce permanent damage to the device: a
typical failure is the breakdown of thin oxides,
which causes high leakage current and sometimes
shorts.
Latchup is another typical phenomenon occurring
in integrated circuits: unwanted turning on of para-
sitic bipolar structures, or silicon-controlled rectifi-
ers (SCR), may overheat and rapidly destroy the
device. These unintentional structures are com-
posed of P and N regions which work as emitters,
bases and collectors of parasitic bipolar transis-
tors: the bulk resistance of the silicon in the wells
and substrate act as resistors on the SCR struc-
ture. Applying voltages below VSS or above VDD,
and when the level of current is able to generate a
P
N
IN
OUT
VDD
VSS
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST92F120V6T | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64 |
| ST92F120V9T | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64 |
| ST92F124R1T6 | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64 |
| ST92F150JDV1QCE | 16-BIT, FLASH, 5 MHz, MICROCONTROLLER, PQFP100 |
| ST92F250CV2QC | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST92F120V1Q7 | 功能描述:8位微控制器 -MCU Flash 128K SPI/I2C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST92F120V9Q7 | 功能描述:8位微控制器 -MCU RO 511-ST92F150CV1QB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST92F124R9TB | 功能描述:8位微控制器 -MCU Flash 64K SCI/SPI/I2 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST92F124V1QB | 功能描述:8位微控制器 -MCU Flash 128K 2SCI/SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST92F124V1T6 | 功能描述:8位微控制器 -MCU 8/16-BIT SINGLE VOLT RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。