參數(shù)資料
型號: STCD23100F35F
廠商: STMICROELECTRONICS
元件分類: 時鐘及定時
英文描述: 2310 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA12
封裝: 1.20 X 1.60 MM, 0.40 MM PITCH, ROHS COMPLIANT, FLIP CHIP-12
文件頁數(shù): 7/39頁
文件大?。?/td> 1948K
代理商: STCD23100F35F
STCD22x0, STCD23x0, STCD24x0
Application information
Doc ID 15400 Rev 2
4.5
Phase noise
Phase noise is a frequency domain phenomenon and is a critical specification in reference
clocks. It is illustrated by a continuous spreading of the energy of the wave mainly caused by
random noise. The phase noise is normally specified with a unit of dBc/Hz at a given offset
in frequency (for example, 10 kHz) from the carrier wave (for example, 26 MHz). The value
of the phase noise is the difference of the power contained within 1 Hz bandwidth of the
offset frequency to the power at the carrier frequency. The total phase noise of the clock tree
is obtained by adding the additive phase noise of STCD22x0, STCD23x0 and STCD24x0
and the phase noise of the clock source (for example, TCXO) in power which is illustrated in
Equation 1
where:
PNT is the total phase noise in dBc/Hz
PNC is the additive phase noise of STCD22x0, STCD23x0 and STCD24x0 and
PNX is the phase noise of clock source
Make sure the total phase noise is kept within the phase noise requirement of each
application PNA. The user should choose the right TCXO with proper phase noise to meet
the requirement.
A
10
PN
10
PN
T
PN
)
10
log(
10
PN
X
C
<
+
=
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