
Introduction
1.2 Features
Samsung ASIC
1-3
STD150
Standard Interface IP
- PCI 2.1 compliant, 33/66MHz, 5V tolerant
- USB 1.1 compliant, full speed/low speed, 3.3V
- SSTL2 Class-I and II SDRAM interface, up to 200MHz
- ATA4/UDMA66, 3.3V, 5V tolerant
- AGP 2.0 compliant, 66MHz @ 1X, 133MHz @ 2X, 266MHz @ 4X
- PECL, 200MHz single ended, 500MHz differential point-to-point ATM
interface
- HSTL, 300MHz, 1.5V SRAM interface with programmable output impedance
control
- Hot Swap PCI - 1V pre-charge, VIO pre-charge
- PCI-X, 1.0 compliant, 133MHz, 3.3V
Fully Integrated CAD software and EDA support
- Logic synthesis: Synopsys Design compiler
- Physical synthesis: Synopsys Physical compiler
- Logic simulation: Cadence Verilog XL, Cadence NC-Verilog/VHDL,
Mentor ModelSim-VHDL, Mentor ModelSim-Verilog, Synopsys VCS.
- DFT, scan insertion and ATPG: Synopsys TestGen, Synopsys TestCompiler,
Synopsys TetraMax, Mentor Fastscan.
- Static timing analysis: Synopsys PrimeTime
- RC analysis: Avant! Star-RCXT
- Power analysis: Synopsys DesignPower, Sequence Watt Watcher,
CubicPower (Samsung in-house tool).
- Formal verification: Synopsys Formality, Avant! Design VERIFYer,
Verplex Tuxedo-LEC
- Fault simulation: Cadence Verifault
- Delay calculator: CubicDelay (Samsung in-house tool).
- Floor planner: Avant! PlanerPL, CubicPlan (Samsung in-house tool).
- Place and Route: Avant! Apollo, Cadence Silicon Ensemble
- DRC and LVS: Dracula, Hercules, Calibre
Easy and Accurate Clock Tree Insertion
- 12 user selectable clock tree cells
- Accurate pre-layout and post-layout correlation
- Insertion delay, skew, transition time management
- Clock tree information file generation
- Tightly coupled with in-house delay calculator, CubicDelay.
For more information on the CTC flow, refer to "Clock Analysys Flow (with CTC)
User Guide for CubicDelay" included in the Samsung Design Kit.