參數(shù)資料
型號(hào): STE10/100E
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128
封裝: 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128
文件頁(yè)數(shù): 17/66頁(yè)
文件大?。?/td> 396K
代理商: STE10/100E
STE10/100A
24/66
Table 6. Control/Status register description
CSR14(offset = 70h), WPDR –Wake-up Pattern Data Register
Offset
31
16
15
8
7
0
0000h
Wake-up pattern 1 mask bits 31:0
0004h
Wake-up pattern 1 mask bits 63:32
0008h
Wake-up pattern 1 mask bits 95:64
000ch
Wake-up pattern 1 mask bits 127:96
0010h
CRC16 of pattern 1
Reserved
Wake-up pattern 1 offset
0014h
Wake-up pattern 2 mask bits 31:0
0018h
Wake-up pattern 2 mask bits 63:32
001ch
Wake-up pattern 2 mask bits 95:64
0020h
Wake-up pattern 2 mask bits 127:96
0024h
CRC16 of pattern 2
Reserved
Wake-up pattern 2 offset
0028h
Wake-up pattern 3 mask bits 31:0
002ch
Wake-up pattern 3 mask bits 63:32
0030h
Wake-up pattern 3 mask bits 95:64
0034h
Wake-up pattern 3 mask bits 127:96
0038h
CRC16 of pattern 3
Reserved
Wake-up pattern 3 offset
003ch
Wake-up pattern 4 mask bits 31:0
0040h
Wake-up pattern 4 mask bits 63:32
0044h
Wake-up pattern 4 mask bits 95:64
0048h
Wake-up pattern 4 mask bits 127:96
004ch
CRC16 of pattern 4
Reserved
Wake-up pattern 4 offset
0050h
Wake-up pattern 5 mask bits 31:0
0054h
Wake-up pattern 5 mask bits 63:32
0058h
Wake-up pattern 5 mask bits 95:64
005ch
Wake-up pattern 5 mask bits 127:96
0060h
CRC16 of pattern 5
Reserved
Wake-up pattern 5 offset
1. Offset value is from 0-255 (8-bit width).
2. To load the whole wake-up frame filtering information, consecutive 25 long words write operation to CSR14 should be done.
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