參數(shù)資料
型號: STK11C68-5L35M
廠商: Electronic Theatre Controls, Inc.
英文描述: CMOS NV SRAM
中文描述: 的CMOS非易失SRAM
文件頁數(shù): 7/10頁
文件大小: 59K
代理商: STK11C68-5L35M
STK11C68-M
4-37
#1
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
(V
CC
= 5.0V
±
10%)
STORE/RECALL CYCLE
22
t
AVAV
t
RC
STORE/RECALLInitiation Cycle Time
35
45
55
ns
23
t
ELQZp
Chip Enable to Output Inactive
75
75
85
ns
24
t
ELQXS
t
STOREq
STORECycle Time
10
10
10
ms
25
t
ELQXR
t
RECALLr
RECALL Cycle Time
20
20
20
μ
s
26
t
AVELNs
t
AE
Address Set-up to Chip Enable
0
0
0
ns
27
t
ELEHNs,t
t
EP
Chip Enable Pulse Width
25
35
45
ns
28
t
EHAXNs
t
EA
Chip Disable to Address Change
0
0
0
ns
SYMBOLS
STK11C68-35M
STK11C68-45M
STK11C68-55M
NO.
PARAMETER
UNITS
Note p: Once the software STORE
or RECALLcycle is initiated, it completes automatically, ignoring all inputs.
Note q: Note that STOREcycles (but not RECALLs) are aborted by V
CC
< 4.0V (STORE inhibit).
Note r: A RECALL cycle is initiated automatically at power up when V
CC
exceeds 4.0V. t
RECALL
s measured from the point at which V
CC
exceeds 4.5V.
Note s: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence.
Note t: If the Chip Enable Pulse Width is less than t
ELQV
(see
READ CYCLE
#2) but greater than or equal to t
ELEHN
, then the data may not be valid at the end of
the low pulse, however the STOREor RECALLwill still be initiated.
Note u: W must be
HIGH
when E is
LOW
during the address sequence in order to initiate a nonvolatile cycle. G may be either
HIGH
or
LOW
throughout.
Addresses #1 through #6 are found in the
MODE SELECTION
table. Address #6 determines whether the STK11C68-M performs a STORE
or RECALL
.
Note v: E must be used to clock in the address sequence for the Software STORE and RECALL cycles.
STORE/RECALL CYCLE
u,v
ADDRESS
E
DATA OUT
DATA VALID
ADDRESS #6
ADDRESS #1
DATA VALID
HIGH IMPEDANCE
22
t
AVAV
22
t
AVAV
26
t
AVELN
27
t
ELEHN
28
t
EHAXN
24
t
STORE
25
t
RECALL
23
t
ELQZ
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