參數(shù)資料
型號: STPCI0166BTI3
廠商: 意法半導體
元件分類: 微處理器
英文描述: PC Compatible Embedded Microprocessor
中文描述: PC兼容嵌入式微處理器
文件頁數(shù): 35/55頁
文件大?。?/td> 787K
代理商: STPCI0166BTI3
ELECTRICAL SPECIFICATIONS
35/55
Issue 1.1
4.4 DC CHARACTERISTICS
Notes:
1. MHz ratings refer to CPU clock frequency.
2. Not yet released.
4.5 AC CHARACTERISTICS
Table 4-5 through Table 4-14 list
characteristics including
setup requirements, input hold requirements and
output float delays. These measurements are
based on the measurement points identified in
Figure 4-1. The rising clock edge reference level
VREF , and other reference levels are shown in
Table 4-4 below for the STPC Industrial. Input or
output signals must cross these levels during
testing.
the AC
input
output delays,
Figure 4-1 shows output delay (A and B) and
input setup and hold times (C and D). Input setup
and hold times (C and D) are specified minimums,
defining the smallest acceptable sampling window
a synchronous input signal must be stable for
correct operation.
Table 4-2. DC Characteristics
Recommended Operating conditions : VDD = 3.3V
±
0.3V, Tcase = 0 to 100
°
C unless otherwise specified
Symbol
V
DD
P
DD
H
CLK
V
DAC
V
OL
V
OH
V
ILD
Parameter
Test conditions
Min
3.0
Typ
3.3
3.2
Max
3.6
3.9
80
1.255
0.5
Unit
V
W
Mhz
V
V
V
V
V
V
V
μ
A
pF
pF
pF
Operating Voltage
Supply Power
Internal Clock
DAC Voltage Reference
Output Low Voltage
Output High Voltage
Input Low Voltage
V
DD
= 3.3V, H
CLK
= 66Mhz
(Note 1)
1.215
1.235
I
Load
=1.5 to 8mA depending of the pin
I
Load
=-0.5 to -8mA depending of the pin
Except XTALI
XTALI
Except XTALI
XTALI
Input, I/O
(Note 2)
(Note 2)
(Note 2)
2.4
-0.3
-0.3
2.1
2.35
-5
0.8
0.5
V
IHD
Input High Voltage
V
DD
+0.3
V
DD
+0.3
5
I
LK
C
IN
C
OUT
C
CLK
Input Leakage Current
Input Capacitance
Output Capacitance
Clock Capacitance
Table 4-3. RAMDAC DC Specification
Symbol
Vref
INL
DNL
FS
FSR
LSB
Zero
Compare
Parameter
Min
1.00V
-
-
-
14.00 mA
54uA
0.95mA
-
Nom
1.12V
-
-
-
16.50mA
63uA
1.44mA
-
Max
1.24V
2 lsb
1lsb
20mA
19.00 mA
72uA
1.90mA
+/- 5%
Voltage Reference
Integrated Non Linear Error
Differentiated Non Linear Error
Full Scale
Full Scale Range
Least Significant Byte Size
Zero Scale @ 7.5IRE Mode
DAC to DAC matching
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