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參數(shù)資料
| 型號(hào)： | STPCI0180BTI3 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 微處理器 |
| 英文描述： | PC Compatible Embedded Microprocessor |
| 中文描述： | PC兼容嵌入式微處理器 |
| 文件頁(yè)數(shù)： | 28/55頁(yè) |
| 文件大?。?/td> | 787K |
| 代理商： | STPCI0180BTI3 |
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PIN DESCRIPTION
28/55
Issue 1.1
HSYNC
Horizontal Synchronisation Pulse. This is
the horizontal synchronization signal from the
VGA controller.
VREF_DAC
DAC Voltage reference. This pin is
an input driving the digital to analog converters.
This allows an external voltage reference source
to be used.
RSET
Resistor Current Set. This is the reference
current input to the RAMDAC. Used to set the full-
scale output of the RAMDAC.
COMP
Compensation.This is the RAMDAC com-
pensation pin. Normally, an external capacitor
(typically 10nF)is connected between this pin and
V
DD
to damp oscillations.
DDC[1:0]
Direct Data Channel Serial Link. These
bidirectional pins are connected to CRTC register
3Fh to implement DDC capabilities. They conform
to I
2
C electrical specifications, they have open-
collector output drivers which are internally con-
nected to V
DD
through pull-up resistors.
They can instead be used for accessingI C devic-
es on board. DDC1 and DDC0 correspond to SCL
and SDA respectively.
3.2.14 FLAT PANEL INTERFACE SIGNALS
(Combined with Serial 1)
FPFRAME,
Vertical Sync. pulse Output.
FPLINE,
Horizontal Sync. Pulse Output.
DE,
Data Enable.
R5-0,
Red Output.
G5-0,
Green Output.
B5-0,
Blue Output
ENAVDD
Enable VDD of Flat Panel.
ENVCC
Enable VCC of Flat Panel.
PWM
PWM Back-Light Control.
3.2.15 MISCELLANEOUS
SPKRD
Speaker Drive. This is the output to the
speaker and is the AND of the counter 2 output
with bit 1 of Port 61h and drives anexternal speak-
er driver. This output should be connected to a
7407 type high voltage driver.
SCAN_ENABLE
Reserved This pin is reserved
for Test and Miscellaneous functions. It has to be
set to ‘0’ or connected to ground in normal opera-
tion.
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