參數(shù)資料
型號(hào): STR751FR0
廠商: 意法半導(dǎo)體
元件分類: ADC
英文描述: Zener Diode; Application: General; Pd (mW): 400; Vz (V): 29.02 to 30.51; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: MHD
中文描述: 的ARM7TDMI - S⑩32位微控制器的閃存,新措施,3性病16位定時(shí)器,PWM定時(shí)器,快速的10位ADC和I2C,UART的,過磷酸鈣,USB和CAN
文件頁數(shù): 14/84頁
文件大?。?/td> 997K
代理商: STR751FR0
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Pin description
21/84
91
A4
59
A3
P1.04 / PWM3N /
ADC_IN9
I/O
TT
X
XO4
X
Port 1.04
PWM: PWM3
complementary
output(4)
ADC: analog
input 9
92
A3
P1.14 /
ADC_IN15
I/O
TT
X
XO8
X
Port 1.14
ADC: analog input 15
93
A2
P1.13 /
ADC_IN14
I/O
TT
X
XEIT13
O8
X
Port 1.13
ADC: analog input 14
94
D5
P1.01 / TIM0_TI2
I/O
TT
X
XO2
X
Port 1.01
TIM0: Input Capture / trigger /
external clock 2 (remappable to
P0.05)(8)
95
E6
P1.00 /
TIM0_OC2
I/O
TT
X
XO2
X
Port 1.00
TIM0: Output compare 2
(remappable to P0.04)(8)
96
C4
60
C4
V18
S
Stabilization for main voltage regulator. Requires
external capacitors 33nF between V18 and VSS18.
See Figure 4.
To be connected to the 1.8V external power supply
when embedded regulators are not used.
97
D4
61
C5
VSS18
S
Ground Voltage for the main voltage regulator.
98
D3
62
A2
VSS_IO
S
Ground Voltage for digital I/Os
99
C3
63
B2
VDD_IO
S
Supply Voltage for digital I/Os
100
A1
64
A1
P0.03 / TIM2_TI1
/ ADC_IN1
I/O
TT
X
XO2
X
Port 0.03
TIM2: Input
Capture / trigger
/ external clock 1
ADC: analog
input 1
1.
For STR755FVx part numbers, the USB pins must be left unconnected.
2.
The non available pins on LQPFP64 and LFBGA64 packages are internally tied to low level.
3.
None of the I/Os are True Open Drain: when configured as Open Drain, there is always a protection diode between the I/O
pin and VDD_IO.
4.
In the 100-pin package, this Alternate Function is duplicated on two ports. You can configure one port to use this AF, the
other port is then free for general purpose I/O (GPIO), external interrupt/wake-up lines, or analog input (ADC_IN) where
these functions are listed in the table.
5.
It is mandatory that the NJTRST pin is reset to ground during the power-up phase. It is recommended to connect this pin to
NRSTOUT pin (if available) or NRSTIN.
6.
After reset, these pins are enabled as JTAG alternate function see (Port reset state on page 16). To use these ports as
general purpose I/O (GPIO), the DBGOFF control bit in the GPIO_REMAP0R register must be set by software (in this case,
debugging these I/Os via JTAG is not possible).
7.
There are two different TQFP and BGA 64-pin packages: in the first one, pins 41 and 42 are mapped to USB DN/DP while
for the second one, they are mapped to P0.15/CAN_TX and P0.14/CAN_RX.
8.
For details on remapping these alternate functions, refer to the GPIO_REMAP0R register description.
Table 6.
STR750F pin description (continued)
Pin n°
Pin name
Ty
p
e
Input
Output
Usa
b
le
i
n
Stan
db
y
Main
function
(after
reset)
Alternate function
LQ
FP100
(1)
LFBGA100
(1
)
LQ
FP64
(2
)
LFBGA6
4
(2
)
Input
Le
vel
floating
pu
/p
d
Ext.
int
/W
ake-up
Capabi
lity
OD
(3)
PP
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