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參數(shù)資料
| 型號： | STR91XF |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | ADC |
| 英文描述： | ARM966E-S 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC Motor Control, 4 Timers, ADC, RTC, DMA |
| 中文描述： | ARM966E - ? 16/32位閃存微控制器與以太網(wǎng)，USB，加拿大，交流電機(jī)控制，4個(gè)計(jì)時(shí)器，模數(shù)轉(zhuǎn)換器，RTC和DMA的 |
| 文件頁數(shù)： | 11/72頁 |
| 文件大?。?/td> | 664K |
| 代理商： | STR91XF |
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STR91xF
Functional overview
19/72
2.13
System supervisor
The STR91xF monitors several system and environmental inputs and will generate a global
reset, a system reset, or an interrupt based on the nature of the input and configurable settings.
A global reset clears all functions on the STR91xF, a system reset will clear all but the Clock
Control Unit (CCU) settings and the system status register. At any time, firmware may reset
individual on-chip peripherals. System supervisor inputs include:
●
GR: CPU voltage supply (VDD) drop out or brown out
●
GR: I/O voltage supply (VDDQ) drop out or brown out
●
GR: Power-Up condition
●
SR: Watchdog timer timeout
●
SR: External reset pin (RESET_INn)
●
SR: JTAG debug reset command
Note:
GR: means the input causes Global Reset, SR: means the input causes System Reset
The CPU may read a status register after a reset event to determine if the reset was caused by
a watchdog timer timeout or a voltage supply drop out. This status register is cleared only by a
power up reset.
2.13.1 Supply voltage brownout
Each operating voltage source (VDD and VDDQ) is monitored separately by the Low Voltage
Detect (LVD) circuitry. The LVD will generate an early warning interrupt to the CPU when
voltage sags on either VDD or VDDQ voltage inputs. This is an advantage for battery powered
applications because the system can perform an orderly shutdown before the batteries become
too weak. The voltage trip point to cause a brown out interrupt is typically 0.25V above the LVD
dropout thresholds that cause a reset.
CPU firmware may prevent all brown-out interrupts by writing to interrupt mask registers at run-
time.
2.13.2 Supply voltage dropout
LVD circuitry will always cause a global reset if the CPU’s VDD source drops below it’s fixed
threshold of 1.4V.
However, the LVD trigger threshold to cause a global reset for the I/O ring’s VDDQ source is set
to one of two different levels, depending if VDDQ will be operated in the range of 2.7V to 3.3V, or
3.0V to 3.6V. If VDDQ operation is at 2.7V to 3.3V, the LVD dropout trigger threshold is 2.4V. If
VDDQ operation is 3.0V and 3.6V, the LVD threshold is 2.7V. The choice of trigger level is made
by STR91xF device configuration software from STMicroelectronics, and is programmed into
the STR91xF device along with other configurable items through the JTAG interface when the
Flash memory is programmed.
CPU firmware may prevent some LVD resets if desired by writing a control register at run-time.
Firmware may also disable the LVD completely for lowest-power operation when an external
LVD device is being used.
2.13.3 Watchdog timer
The STR91xF has a 16-bit down-counter (not one of the four TIM timers) that can be used as a
watchdog timer or as a general purpose free-running timer/counter. The clock source is the
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