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參數(shù)資料
| 型號(hào)： | SX28ACDP |
| 英文描述： | IC-8-BIT MCU |
| 中文描述： | 集成電路8位微控制器 |
| 文件頁數(shù)： | 27/42頁 |
| 文件大?。?/td> | 312K |
| 代理商： | SX28ACDP |
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1999 Scenix Semiconductor, Inc. All rights reserved.
- 27 -
www.scenix.com
SX18AC / SX20AC / SX28AC
15.0
As mentioned earlier, the SX family of devices uses a
modified Harvard architecture with memory-mapped
input/output. The device also has a RISC type architec-
ture in that there are 43 single-word basic instructions.
The instruction set contains byte-oriented file register, bit-
oriented file register, and literal/control instructions.
Working register W is one of the CPU registers, which
serves as a pseudo accumulator. It is a pseudo accumu-
lator in a sense that it holds the second operand,
receives the literal in the immediate type instructions, and
also can be program-selected as the destination register.
The bank of 31 file registers can also serve as the pri-
mary accumulators, but they represent the first operand
and may be program-selected as the destination regis-
ters.
15.1
Instruction Set Features
1. All single-word (12-bit) instructions for compact code
efficiency.
2. All instructions are single cycle except the jump type in-
structions (JMP, CALL) and failed test instructions
(DECSZ fr, INCSZ fr, SB bit, SNB bit), which are two-
cycle.
3. A set of File registers can be addressed directly or indi-
rectly, and serve as accumulators to provide first oper-
and; W register provides the second operand.
4. Many instructions include a destination bit which se-
lects either the register file or the accumulator as the
destination for the result.
5. Bit manipulation instructions (Set, Clear, Test and Skip
if Set, Test and Skip if Clear).
6. STATUS Word register memory-mapped as a register
file, allowing testing of status bits (carry, digit carry, ze-
ro, power down, and timeout).
7. Program Counter (PC) memory-mapped as register file
allows W to be used as offset register for indirect ad-
dressing of program memory.
8. Indirect addressing data pointer FSR (file select regis-
ter) memory-mapped as a register file.
9. IREAD instruction allows reading the instruction from
the program memory addressed by W and upper four
bits of MODE register.
10.Eight-level, 11-bit push/pop hardware stack for sub-
routine linkage using the Call and Return instructions.
11.Six addressing modes provide great flexibility.
15.2
Instruction Execution
An instruction goes through a four-stage pipeline to be
executed (Figure 15-1). The first instruction is fetched
from the program memory on the first clock cycle. On the
second clock cycle, the first instruction is decoded and
the second instruction is fetched. On the third clock cycle,
the first instruction is executed, the second instruction is
decoded, and the third instruction is fetched. On the
fourth clock cycle, the first instruction’s results are written
to its destination, the second instruction is executed, the
third instruction is decoded, and the fourth instruction is
INSTRUCTION SET
fetched. Once the pipeline is full, instructions are exe-
cuted at the rate of one per clock cycle.
Instructions that directly affect the contents of the pro-
gram counter (such as jumps and calls) require that the
pipeline be cleared and subsequently refilled. Therefore,
these instruction take more than one clock cycle.
The instruction execution time is derived by dividing the
oscillator frequency by either one (turbo mode) or four
(non-turbo mode). The divide-by factor is selected
through the FUSE Word register.
15.3
The device support the following addressing modes:
Data Direct
Data Indirect
Immediate
Program Direct
Program Indirect
Relative
Both direct and indirect addressing modes are available.
The INDF register, though physically not implemented, is
used in conjunction with the indirect data pointer (FSR) to
perform indirect addressing. An instruction using INDF as
its operand field actually performs the operation on the
register pointed by the contents of the FSR. Conse-
quently, processing two multiple-byte operands requires
alternate loading of the operand addresses into the FSR
pointer as the multiple byte data fields are processed.
Examples:
Direct addressing:
Addressing Modes
Indirect Addressing:
Figure 15-1.
Pipeline and Clock Scheme
mov
RA,#01
;move “1” to RA
mov
FSR,#RA
;FSR = address of RA
mov
INDF,#$01
;move “1” to RA
Fetch
Decode
Execute
Write
Clock
Cycle
1
Clock
Cycle
2
Clock
Cycle
3
Clock
Cycle
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SX28ACSO | SX28ACSO:IC-SM-8-BIT MCU |
| SX18AC75DP | IC-8-BIT MCU |
| SX18AC75SO | IC-SM-8-BIT MCU |
| SX18ACDP | IC-8-BIT MCU |
| SX18ACSO | IC-SM-8 BIT MCU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SX28AC-I/SO | 功能描述:8位微控制器 -MCU U 619-SX28AC/SS RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SX28ACISS | 功能描述:8位微控制器 -MCU SSOP UBICOM MICRO RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| SX28ACSO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX28ACSO:IC-SM-8-BIT MCU |
| SX28AD100-I/DP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
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