www.semtech.com/products/ Page 49 ADVANCED COMMUNICATIONS & SENSING DATASHEET SX8724C ZoomingADC fo" />
參數(shù)資料
型號: SX8724CWLTDT
廠商: Semtech
文件頁數(shù): 44/67頁
文件大小: 0K
描述: IC DAS ADC 16BIT I2C/SRL
標準包裝: 1
系列: ZoomingADC™
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
輸入類型: 差分
輸出類型: 數(shù)字
接口: I²C
安裝類型: 表面貼裝
封裝/外殼: 16-WQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-MLPQ-EP(4x4)
包裝: *
其它名稱: SX8724CWLTDTDKR
www.semtech.com/products/
Page 49
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
SX8724C
ZoomingADC for sensing data acquisition
Revision 1.01
January 2011
Semtech
show short voltage spikes at the frequency fs, but these will not influence the measurement. Whereas if the bandwidth
of the node is lower, no spikes will arise, but a small offset can be generated by the integration of the charges
generated by the switched capacitors, this corresponds to the mean impedance effect.
Notes:
(1)
One can increase the mean input impedance of the ZoomingADC by lowering the acquisition clock fs.
(2)
One can increase the mean input impedance of the ZoomingADC by decreasing the gain of the first enabled amplifier.
(3)
One can increase the effective input impedance of the ZoomingADC by having a source with a high electrical bandwidth (sensor electri-
cal bandwidth much higher than fs).
11.2 Frequency Response
The incremental ADC is an over-sampled converter with two main blocks: an analog modulator and a low-pass digital
filter. The main function of the digital filter is to remove the quantization noise introduced by the modulator. This filter
determines the frequency response of the transfer function between the output of the ADC and the analog input VIN.
Notice that the frequency axes are normalized to one elementary conversion period OSR / fs. The plots of Figure 28,
page 50 also show that the frequency response changes with the number of elementary conversions NELCONV
performed. In particular, notches appear for NELCONV >= 2 These notches occur at:
and are repeated every fs / OSR.
Information on the location of these notches is particularly useful when specific frequencies must be filtered out by the
acquisition system. This chip has no dedicated 50/60 Hz rejection filtering but some rejection can be achieved by using
Equation 27 and setting the appropriate values of OSR, fs and NELCONV.
For
Equation 27
Table 38. 50/60 Hz Line Rejection Examples
Rejection [Hz]
fNOTCH [Hz]
fs [kHz]
OSR [-]
NELCONV [-]
60
61
125
1024
2
61
250
1024
4
61
500
1024
8
50
53
62.5
1024
8
46
62.5
1024
4
46
125
1024
8
f
NOTCH
if
s
OSR N
ELCONV
-------------------------------------
=
i
12
… N
ELCONV
1
()
,,
=
Not
Recommended
for
New
Designs
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