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參數(shù)資料
| 型號(hào)： | SX8725E083TRT |
| 廠商： | Semtech |
| 文件頁(yè)數(shù)： | 31/53頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS PRESSURE/TEMP SENS 12MLPD |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ZoomingADC™ |
| 類(lèi)型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 輸入類(lèi)型： | 差分 |
| 輸出類(lèi)型： | 數(shù)字 |
| 接口： | I²C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 12-WFDFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 12-MLPD |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 配用： | XE8000EV121-ND - BOARD EVAL FOR SX8723/24 |
| 其它名稱： | SX8725E083DKR |
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ADVANCED COMMUNICATIONS & SENSING
V1.8 2009 Semtech Corp.
www.semtech.com
37
SX8725
ZoomingADC for Pressure and Temperature Sensing
PGA Settling or Input Channel Modifications
PGAs are reset after each writing operation to registers RegAcCfg1-5. Similarly, input channels are switched
after modifications of AMUX[4:0] or VMUX. To ensure precise conversion, the ADC must be started after a PGA
or inputs common-mode stabilization delay. This is done by writing bit START several cycles after PGA settings
modification or channel switching. Delay between PGA start or input channel switching and ADC start should be
equivalent to OSR (between 8 and 1024) number of cycles. This delay does not apply to conversions made
without the PGAs.
If the ADC is not settled within the specified period, there is most probably an input impedance problem (see
previous section).
PGA Gain & Offset, Linearity and Noise
Hereafter are a few design guidelines that should be taken into account when using the ZoomingADC:
1.
Keep in mind that increasing the overall PGA gain, or "zooming" coefficient, improves linearity but
degrades noise performance.
2.
Use the minimum number of PGA stages necessary to produce the desired gain ("zooming") and offset.
Bypass unnecessary PGAs.
3.
Put most gain on PGA3 and use PGA2 and PGA1 only if necessary.
4.
PGA3 should be always ON for best linearity.
5.
For low-noise applications where power consumption is not a primary concern, maintain the largest bias
currents in the PGAs and in the ADC; i.e. set IB_AMP_PGA[1:0] = IB_AMP_ADC[1:0] = '11'.
6.
For lowest output offset error at the output of the ADC, bypass PGA2 and PGA3. Indeed, PGA2 and
PGA3 typically introduce an offset of about 5 to 10 LSB (16 bit) at their output. Note, however, that the
ADC output offset is easily calibrated out by software.
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