參數(shù)資料
型號: SY100E111JYTR
廠商: MICREL INC
元件分類: 時鐘及定時
英文描述: 1:9 DIFFERENTIAL CLOCK DRIVER WITH ENABLE
中文描述: 100E SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28
封裝: LEAD FREE, PLASTIC, LCC-28
文件頁數(shù): 1/4頁
文件大小: 75K
代理商: SY100E111JYTR
1
SY10E111
SY10E111
SY100E111
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
BLOCK DIAGRAM
IN
V
BB
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
Q
6
Q
6
Q
7
Q
7
Q
8
Q
8
IN
EN
FEATURES
I
Low skew
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
Guaranteed skew limits
I
Differential design
I
V
BB
output
I
Enable input
I
Fully compatible with industry standard 10KH, 100K
I/O levels
I
75K
input pulldown resistors
I
Fully compatible with ON Semiconductor
MC10E/100E111
I
Available in 28-pin PLCC package
The SY10/100E111 are low skew 1-to-9 differential
drivers designed for clock distribution in new, high-
performance ECL systems. They accept one differential or
single-ended input, with V
BB
used for single-ended
operation. The signal is fanned out to nine identical
differential outputs. An enable input is also provided such
that a logic HIGH disables the device by forcing all Q
outputs LOW and all /Q outputs HIGH.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the E111 shares a common set of “basic”
processing with the other members of the ECLinPS
family, wafer characterization at the point of device
personalization allows for tighter control of parameters,
including propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50
, even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same V
CCO
as the pair(s) being used on that side) in order
to maintain minimum skew.
The V
BB
output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using V
BB
for this purpose, it is
recommended that V
BB
is decoupled to V
CC
via a 0.01
μ
F
capacitor.
1:9 DIFFERENTIAL CLOCK
DRIVER WITH ENABLE
DESCRIPTION
Rev.: E
Issue Date:
Amendment: /0
March 2006
Pin
Function
IN, /IN
Differential Input Pair
/EN
Enable Input
Q0, /Q0 — Q8, /Q8
Differential Outputs
V
BB
V
CCO
V
BB
Output
V
CC
to Output
PIN NAMES
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