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參數(shù)資料
| 型號： | SY100E131JY |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-BIT D FLIP-FLOP |
| 中文描述： | 100E SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28 |
| 封裝： | LEAD FREE, PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 72K |
| 代理商： | SY100E131JY |
1
SY10E131
SY10E131
SY100E131
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
FEATURES
I
1100MHz min. toggle frequency
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
Differential output
I
Individual and common clocks
I
Indivldual asynchronous reset
I
Paired asynchronous sets
I
Fully compatible with Industry standard 10KH,
100K ECL levels
I
Internal 75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E131
I
Available in 28-pin PLCC package
4-BIT D
FLIP-FLOP
The SY10/100E131 are high-speed quad master slave
D-type flip-flops with differential outputs designed for use
in new, high-performance ECL systems. The flip-flops may
be individually clocked by holding C
C
(Common Clock) at
a logic LOW and then using the four individual CE (Clock
Enable CE
0
–CE
3
) inputs to accomplish such clocking.
Alternatively, all four flip-flops can be clocked in common
by holding the CE inputs LOW and then using C
C
to clock
the data. In the common clock mode, the CE input acts as
a control that passes the C
C
signal to the flip-flop. Data is
clocked into the flip-flop on the rising edge of the output of
the logical OR operation between CE and C
C
(data enters
the master when both C
C
and CE are LOW and data
transfers to the slave when either CE or C
C,
or both, go
HIGH).
Asynchronous set and reset controls are provided. The
reset controls are individual and the set controls are
pairwise.
Pin
Function
D
0
-D
3
Data Inputs
CE
0
-CE
3
Clock Enables (Individual)
R
0
-R
3
Resets
C
C
Common Clock
S
03
, S
12
Sets (paired)
Q
0
-Q
3
True Outputs
Q
0
-Q
3
Inverting Outputs
V
CCO
V
CC
to Output
PIN NAMES
DESCRIPTION
Rev.: H
Issue Date:
Amendment: /0
March 2006
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY100E131JYTR | 4-BIT D FLIP-FLOP |
| SY100E136JZ | 6-BIT UNIVERSAL UP/DOWN COUNTER |
| SY100E136JZTR | 6-BIT UNIVERSAL UP/DOWN COUNTER |
| SY100E137JZ | 8-BIT RIPPLE COUNTER |
| SY100E137JZTR | 8-BIT RIPPLE COUNTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100E131JY TR | 功能描述:觸發(fā)器 4-bit D Flip-Flop (I Temp, Lead Free) RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| SY100E131JYTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:4-BIT D FLIP-FLOP |
| SY100E136 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:6-BIT UNIVERSAL UP/DOWN COUNTER |
| SY100E136JC | 功能描述:IC COUNTER UP/DOWN 6-BIT 28-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 -計數(shù)器，除法器 系列:100E 產(chǎn)品變化通告:1Q2012 Discontinuation 30/Mar/2012 標準包裝:2,500 系列:74HC 邏輯類型:二進制計數(shù)器 方向:上 元件數(shù):1 每個元件的位元數(shù):12 復(fù)位:異步 計時:- 計數(shù)速率:50MHz 觸發(fā)器類型:負邊沿 電源電壓:2 V ~ 6 V 工作溫度:-55°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| SY100E136JC TR | 功能描述:IC COUNTER UP/DOWN 6-BIT 28-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 -計數(shù)器，除法器 系列:100E 產(chǎn)品變化通告:1Q2012 Discontinuation 30/Mar/2012 標準包裝:2,500 系列:74HC 邏輯類型:二進制計數(shù)器 方向:上 元件數(shù):1 每個元件的位元數(shù):12 復(fù)位:異步 計時:- 計數(shù)速率:50MHz 觸發(fā)器類型:負邊沿 電源電壓:2 V ~ 6 V 工作溫度:-55°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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