參數(shù)資料
型號(hào): SY100E171JC TR
廠商: Micrel Inc
文件頁(yè)數(shù): 1/4頁(yè)
文件大?。?/td> 0K
描述: IC MULTIPLEXER 3-BIT 4:1 28-PLCC
標(biāo)準(zhǔn)包裝: 750
系列: 100E
類型: 多路復(fù)用器
電路: 3 x 4:1
獨(dú)立電路: 1
電壓電源: 雙電源
電源電壓: 4.2 V ~ 5.5 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC
包裝: 帶卷 (TR)
其它名稱: SY100E171JCTR
SY100E171JCTR-ND
1
SY10E171
SY100E171
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
s 725ps max. D to output
s Extended 100E VEE range of –4.2V to –5.5V
s Differential outputs
s Split select architecture
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75K
input pulldown resistors
s Fully compatible with Motorola MC10E/100E171
s Available in 28-pin PLCC package
FEATURES
3-BIT 4:1
MULTIPLEXER
The SY10/100E171 offer three 4:1 multiplexers with
differential outputs, designed for use in new, high-
performance ECL systems. The leading 4-bit multiplexer
operation is organized pairwise, with each pair being a 2-
bit multiplexer. Separate select (SEL1A, SEL1B) controls
are provided within each pair. The SEL1A and SEL1B
signals control the leading multiplexers, while the SEL2
signal controls the output multiplexer. The three select
signals can be used to determine which of the four data
inputs will be propagated to the corresponding outputs.
DESCRIPTION
SY10E171
SY100E171
BLOCK DIAGRAM
Pin
Function
D0x–D2x
Data Inputs
SEL1A, SEL1B
First-stage Select Inputs
SEL2
Second-stage Select Input
Q0–Q2
True Output
Q0–Q2
Inverted Output
VCCO
VCC to Output
PIN NAMES
MUX
SEL
2:1
Q0
Q1
Q2
D0a
D0b
SEL1A
D0c
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c
D2d
SEL1B
SEL2
MUX
SEL
2:1
MUX
SEL
2:1
MUX
SEL
2:1
MUX
SEL
2:1
MUX
SEL
2:1
MUX
SEL
2:1
MUX
SEL
2:1
MUX
SEL
2:1
Rev.: E
Amendment: /0
Issue Date:
March 2006
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