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參數(shù)資料
| 型號： | SY100E196JI |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 7TAP 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 38 |
| 系列： | 100E, Precision Edge® |
| 標(biāo)片/步級數(shù)： | 7 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 1.39ns |
| 接頭增量： | 20ps |
| 可用的總延遲： | 1.39ns ~ 3.63ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | -4.2 V ~ -5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC |
| 包裝： | 管件 |
8
Precison Edge
SY10E196
SY100E196
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Typically, the analog input will be driven by an external
DAC to provide a digital control with very fine analog
output steps. The final resolution of the device will be
dependent on the width of the DAC chosen.
To determine the voltage range necessary for the
FTUNE input, the graphs provided should be used. As
an example, if a range of 40ps is selected to cover worst
case conditions and ensure coverage of the digital range,
from the 100E196 graph a voltage range of –3.25V to
–4V would be necessary on the FTUNE pin. Obviously,
there are numerous voltage ranges which can be used
to cover a given delay range.
Users are given the
flexibility to determine which one best fits their design.
Figure 1. Cascading Interconnect Architecture
Cascading Multiple E196s
To increase the programmable range of the E196,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple E196s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E196.
Obviously, cascading multiple PDCs will result in a larger
programmable range; however, this increase is at the
expense of a longer minimum delay.
Figure 1 illustrates the interconnect scheme for
cascading two E196s. As can be seen, this scheme can
easily be expanded for larger E196 chains. The D7 input
of the E196 is the cascade control pin.
With the
interconnect scheme of Figure 1, when D7 is asserted, it
signals the need for a larger programmable range than
is achievable with a single device.
An expansion of the latch section of the block diagram
is pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When
D7 of chip #1 above is low, the cascade output will also
be low, while the cascade bar output will be a logical
high. In this condition, the SET MIN pin of chip #2 will
be asserted and, thus, all of the latches of chip #2 will
be reset and the device will be set at its minimum delay.
Since the RESET and SET inputs of the latches are
overriding, any changes on the A0–A6 address bus will
not affect the operation of chip #2.
Chip #1, on the other hand, will have both SET MIN
and SET MAX de-asserted so that its delay will be
controlled entirely by the address bus A0–A6. If the delay
needed is greater than can be achieved with 31.75 gate
Using the FTUNE Analog Input
The analog FTUNE pin on the E196 device is intended
to enhance the 20ps resolution capabilities of the fully
digital E195.
The level of resolution obtained is
dependent on the number of increments applied to the
appropriate range on the FTUNE pin.
To provide another level of resolution, the FTUNE pin
must be capable of adjusting the delay by greater than
the 20ps digital resolution.
As shown in the provided
graphs, this requirement is easily achieved since a 100ps
delay can be achieved over the entire FTUNE voltage
range.This extra analog range ensures that the FTUNE
pin will be capable, even under worst case conditions, of
covering the digital resolution.
E196
Chip #1
D
4
D
5
D
6
D
7
D
2
D
3
D1
D0
LEN
VEE
IN
VBB
IN
SET
MIN
SET
MAX
CASCADE
EN
CASCADE
VCC
VCCO
Q
VCCO
Q
E196
Chip #2
D
4
D
5
D
6
D
7
D
2
D
3
D1
D0
LEN
VEE
IN
VBB
IN
SET
MIN
SET
MAX
CASCADE
EN
CASCADE
VCC
VCCO
Q
VCCO
Q
ADDRESS BUS (A0 – A6)
A7
Input
Output
LINEAR
INPUT
FTUNE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100E196JITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
| SY100E196JY | 功能描述:延遲線/計(jì)時(shí)元素 Programmable Delay Chip (I Temp, Lead Free) RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| SY100E196JYTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
| SY100E212 | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:3-BIT SCANNABLE REGISTER |
| SY100E212JC | 功能描述:IC REGISTER 3-BIT SCAN 28-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:100E 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標(biāo)準(zhǔn)包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
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