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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� SY100E222LTI
寤�(ch菐ng)鍟嗭細 Micrel Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 6/7闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC CLOCK GEN/BUFF LVPECL 52LQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� 100E, Precision Edge®
椤�(l猫i)鍨嬶細 鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒
PLL锛� 鐒�(w煤)
杓稿叆锛� LVECL锛孡VPECL
杓稿嚭锛� LVPECL
闆昏矾鏁�(sh霉)锛� 1
姣旂巼 - 杓稿叆:杓稿嚭锛� 2:15
宸垎 - 杓稿叆:杓稿嚭锛� 鏄�/鏄�
闋荤巼 - 鏈€澶э細 1.5GHz
闄ゆ硶鍣�/涔樻硶鍣細 鏄�/鐒�(w煤)
闆绘簮闆诲锛� 3 V ~ 3.6 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
灏佽/澶栨锛� 52-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 52-LQFP锛�10x10锛�
鍖呰锛� 鎵樼洡(p谩n)
6
Precision Edge
SY100E222L
Micrel, Inc.
M9999-021511
hbwhelp@micrel.com or (408) 955-1690
SINGLE-ENDED AND DIFFERENTIAL SWINGS
VIN,
VOUT 350mV (Typ.)
Figure 1a. Single-Ended Voltage Swing
VDIFF_IN,
VDIFF_OUT 700mV (Typ.)
Figure 1b. Differential Voltage Swing
TIMING DIAGRAM
Q
/Q
CLK
MR
/CLK
梅2
Q
/Q
梅1
TRUTH TABLE
MR
CLK_SEL
FSEL
Q
00
0
CLK0 梅 1
00
1
CLK0 梅 2
01
0
CLK1 梅 1
01
1
CLK1 梅 2
1X
X
0
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
MS27484T24A4PA CONN PLUG 56POS STRAIGHT W/PINS
MS27497T8B6B CONN HSG RCPT 6POS WALL MT SCKT
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ADF4216BRU-REEL IC PLL FREQ SYNTHESIZER 20-TSSOP
MS3102E36-17P CONN RCPT 47POS BOX MNT W/PINS
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
SY100E222LTI TR 鍔熻兘鎻忚堪:IC CLOCK GEN 1:15 BUFFER 52-LQFP RoHS:鍚� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 鏅�(sh铆)閻�/瑷�(j矛)鏅�(sh铆) - 鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒锛孭LL锛岄牷鐜囧悎鎴愬櫒 绯诲垪:100E, Precision Edge® 妯�(bi膩o)婧�(zh菙n)鍖呰:27 绯诲垪:Precision Edge® 椤�(l猫i)鍨�:闋荤巼鍚堟垚鍣� PLL:鏄� 杓稿叆:PECL锛屾櫠楂� 杓稿嚭:PECL 闆昏矾鏁�(sh霉):1 姣旂巼 - 杓稿叆:杓稿嚭:1:1 宸垎 - 杓稿叆:杓稿嚭:鐒�(w煤)/鏄� 闋荤巼 - 鏈€澶�:800MHz 闄ゆ硶鍣�/涔樻硶鍣�:鏄�/鐒�(w煤) 闆绘簮闆诲:3.135 V ~ 5.25 V 宸ヤ綔婧害:0°C ~ 85°C 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC 鍖呰:绠′欢
SY100E222LTITR 鍒堕€犲晢:MICREL 鍒堕€犲晢鍏ㄧū(ch膿ng):Micrel Semiconductor 鍔熻兘鎻忚堪:3.3V, 1.5GHz 卤1/卤2 DIFFERENTIAL LVECL/LVPECL PROGRAMMABLE CLOCK GENERATOR AND 1:15 FANOUT BUFFER
SY100E222LTY 鍔熻兘鎻忚堪:鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� 1:15 LVPECL Fanout w/ divide-by 1, 2 Dividers (I Temp, Lead Free) RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤�(l猫i)鍨�:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56
SY100E222LTY TR 鍔熻兘鎻忚堪:鏅�(sh铆)閻樼櫦(f膩)鐢熷櫒鍙婃敮鎸佺敘(ch菐n)鍝� 1:15 LVPECL Fanout w/ divide-by 1, 2 Dividers (I Temp, Lead Free) RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤�(l猫i)鍨�:Clock Generators 鏈€澶ц几鍏ラ牷鐜�:14.318 MHz 鏈€澶ц几鍑洪牷鐜�:166 MHz 杓稿嚭绔暩(sh霉)閲�:16 鍗犵┖姣� - 鏈€澶�:55 % 宸ヤ綔闆绘簮闆诲:3.3 V 宸ヤ綔闆绘簮闆绘祦:1 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:QFN-56
SY100E241 鍒堕€犲晢:MICREL 鍒堕€犲晢鍏ㄧū(ch膿ng):Micrel Semiconductor 鍔熻兘鎻忚堪:8-BIT SCANNABLE REGISTER