參數(shù)資料
型號(hào): SY100E241JZ
廠商: MICREL INC
元件分類: 通用總線功能
英文描述: 8-BIT SCANNABLE REGISTER
中文描述: 100E SERIES, 8-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PQCC28
封裝: LEAD FREE, PLASTIC, LCC-28
文件頁(yè)數(shù): 1/4頁(yè)
文件大小: 70K
代理商: SY100E241JZ
1
SY10E241
SY10E241
SY100E241
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
I
1000ps max. CLK to output
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
SHIFT overrides HOLD, /LOAD control
I
Asynchronous Master Reset
I
Pin-compatible with E141
I
Fully compatible with industry standard 10KH,
100K ECL levels
I
Internal 75K
input pulldown resistors
I
Fully compatible with Motorola MC10E/100E241
I
Available in 28-pin PLCC package
FEATURES
8-BIT SCANNABLE
REGISTER
The SY10/100E241 are 8-bit shiftable registers designed
for use in new, high-performance ECL systems. Unlike the
E141, the E241 features internal data feedback organized
such that the SHIFT control overrides the HOLD, /LOAD
control. Thus, the normal operations of HOLD and LOAD
can be toggled with a single control line without the need for
external gating. This configuration also enables switching
to scan mode with the single SHIFT control line.
The eight inputs D
0
–D
7
accept parallel input data, while
S-IN accepts serial input data when in shift mode. Data is
accepted a set-up time before the rising edge of CLK.
Shifting is also accomplished on the rising clock edge. A
HIGH on the Master Reset pin (MR) asychronously resets
all the registers to zero.
DESCRIPTION
Pin
Function
D
0
–D
7
Parallel Data Inputs
S-IN
Serial Data Input
SEL
0
SHIFT Control
SEL
1
HOLD, /LOAD Control
CLK
Clock
MR
Master Reset
Q
0
–Q
7
Data Outputs
V
CCO
V
CC
to Output
PIN NAMES
BLOCK DIAGRAM
R
D
S-IN
Q
R
D
Q
R
D
Q
BITS 1-6
SEL
0
(SHIFT)
CLK
MR
SEL
1
(HOLD/LOAD)
D
0
D
7
D
1
D
6
Q
0
Q
7
Q
1
Q
6
Rev.: F
Issue Date:
Amendment: /0
December 2005
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