參數(shù)資料
型號(hào): SY100E241JZ
廠商: Micrel Inc
文件頁數(shù): 1/4頁
文件大小: 0K
描述: IC REGISTER 8BIT SCAN 28-PLCC
標(biāo)準(zhǔn)包裝: 38
系列: 100E
邏輯類型: 移位寄存器
輸出類型: 標(biāo)準(zhǔn)
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
功能: 通用
電源電壓: 4.2 V ~ 5.5 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC
包裝: 管件
1
SY10E241
SY100E241
Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
s 1000ps max. CLK to output
s Extended 100E VEE range of –4.2V to –5.5V
s SHIFT overrides HOLD, /LOAD control
s Asynchronous Master Reset
s Pin-compatible with E141
s Fully compatible with industry standard 10KH,
100K ECL levels
s Internal 75K
input pulldown resistors
s Fully compatible with Motorola MC10E/100E241
s Available in 28-pin PLCC package
FEATURES
8-BIT SCANNABLE
REGISTER
The SY10/100E241 are 8-bit shiftable registers designed
for use in new, high-performance ECL systems. Unlike the
E141, the E241 features internal data feedback organized
such that the SHIFT control overrides the HOLD, /LOAD
control. Thus, the normal operations of HOLD and LOAD
can be toggled with a single control line without the need for
external gating. This configuration also enables switching
to scan mode with the single SHIFT control line.
The eight inputs D0–D7 accept parallel input data, while
S-IN accepts serial input data when in shift mode. Data is
accepted a set-up time before the rising edge of CLK.
Shifting is also accomplished on the rising clock edge. A
HIGH on the Master Reset pin (MR) asychronously resets
all the registers to zero.
DESCRIPTION
SY10E241
SY100E241
Pin
Function
D0–D7
Parallel Data Inputs
S-IN
Serial Data Input
SEL0
SHIFT Control
SEL1
HOLD, /LOAD Control
CLK
Clock
MR
Master Reset
Q0–Q7
Data Outputs
VCCO
VCC to Output
PIN NAMES
BLOCK DIAGRAM
R
D
S-IN
Q
R
D
Q
R
D
Q
BITS 1-6
SEL0 (SHIFT)
CLK
MR
SEL1 (HOLD/LOAD)
D0
D7
D1 – D6
Q0
Q7
Q1 – Q6
Rev.: F
Amendment: /0
Issue Date:
December 2005
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